High performance VLSI architecture for 3-D discrete wavelet transform

Abstract

This paper presents a memory efficient, high throughput parallel lifting based running three dimensional discrete wavelet transform (3-D DWT) architecture. 3-D DWT is constructed by combining the two spatial and four temporal processors. Spatial processor (SP) apply the two dimensional DWT on a frame, using lifting based 9/7 filter bank through the row rocessor (RP) in row direction and then apply in the colum direction through column processor (CP). To reduce the temporal memory and the latency, the temporal processor (TP) has been designed with lifting based 1-D Haar wavelet filter. The proposed architecture replaced the multiplications by pipeline shift-add operations to reduce the CPD. Two spatial processors works simultaneously on two adjacent frames and provide 2-D DWT coefficients as inputs to the temporal processors. TPs apply the one dimensional DWT in temporal direction and provide eight 3-D DWT coefficients per clock (throughput). Higher throughput reduces the computing cycles per frame and enable the lower power consumption. Implementation results shows that the proposed architecture has the advantage in reduced memory, low power consumption, low latency, and high throughput over the existing designs. The RTL of the proposed architecture is described using verilog and synthesized using 90-nm technology CMOS standard cell library and results show that it consumes 43.42 mW power and occupies an area equivalent to 231.45 K equivalent gate at frequency of 200 MHz. The proposed architecture has also been synthesised for the Xilinx zynq 7020 series field programmable gate array (FPGA). Index TermsIndex Terms : discrete wavelet transform, 3-D DWT, lifting based DWT, VLSI Architecture, flipping structure, strip-based scanning.

Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

“…The mathematical factor consists of arithmetic operations and modules, while a storage component mainly consists of memory transposition which holds the intermediary outcomes. In contrast, lifting based hardware implementation need very less storage space with minimum computation complexity at high cost rate [13], [14]. Hence, developing the new hardware designs which can efficiently perform IC task for IoT based application and similar way lower cost resource constrained are required.…”

“…Then, the process followed by programming which takes benefits of initial values with high frequency zone. Entropy method is the one of the significant process for wavelet image transmission [13]. Another method of image compression is discussed in [14], [15][16][17][18].…”

FPGA Implementation of Image De-noising using Haar Wavelet Transform

“…Srinivasarao and Indrajit [9] present a parallel lifting based architecture of three dimensional architecture of 3D DWT. The parallel lifting scheme has the advantage of high throughput and efficient memory architecture.…”

Efficient VLSI architectures of lifting based 3D discrete wavelet transform

“…A convolution based 3D‐DWT architecture is shown in [6], where the HP and LP FIR filters are used to perform the DWT operation. The 3D discrete Haar WT architectures are explained in [7–9]. The direct form of (5,3) lifting based 3D‐DWT is explained in [10], where four adders and two multipliers are serially connected.…”