Three-dimensional cone filter banks

Bruton, L.T.

doi:10.1109/tcsi.2002.808200

Cited by 78 publications

(49 citation statements)

References 6 publications

(10 reference statements)

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“…Here, the desired fan shape is approximately obtained by parallel connection of N 2-D IIR bandpass subband beam filters (Bruton 2003) having the same axis angle albeit at progressively increasing beam widths, as shown is Fig. 1b.…”

Section: Fan Filterbanksmentioning

confidence: 81%

“…WDFs model analog networks in the digital domain by discretizing scattering parameters (Sparameters) (Bruton 2003). In other words the relationship between voltage (V) and current (I) in one port and three port networks is transformed to continuous-domain wave variables via A = V + I R and B = V − I R, where R > 0 is a quantity known as the port resistance (Madanayake and Bruton 2009).…”

Section: Wave Digital Filtersmentioning

confidence: 99%

“…1b. The sub-bands consisting of temporally bandpass beam WDFs are combined through a perfect-reconstruction polyphase FIR filterbank as described in Bruton (2003). Equation (1) illustrates the transfer function H Fan (z x , z ct ) of a fan filter having N sub-bands, where H I I R (z x , z ct ) is the transfer function of 2-D IIR beam filter and H B P (z ct ) is the temporal bandpass filter employed for band limiting each sub-band (Bruton 2003).…”

Section: Fan Filterbanksmentioning

confidence: 99%

“…We employ design equations in Bruton (2003) to implement bandpass filter H B P (n ct ). The fan-shape is obtained by scaling the beam size of each sub-band beam filter and band Fig.…”

Section: Fan Filterbanksmentioning

confidence: 99%

See 3 more Smart Citations

Fast FPGA-architecture for fan/beam-steering in wave-digital RF aperture arrays

Wijayaratna

Rajapaksha

Madanayake

et al. 2016

Multidim Syst Sign Process

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A digital hardware architecture is proposed for computation of filter coefficients of 1st-and 2nd-order 2-D IIR beam/fan filters, which are capable of enhancement of RF plane-waves based on their direction of arrival, therefore having applications in steerable digital beamformers. Fan filters are designed using the WDF realization, which has superior sensitivity and stability properties since it is derived from the original passive continuousdomain prototype LC ladder network with impedance-matched resistive terminations. The orientation of the fan filter, which is determined by the look-direction of the radio beam, can be altered by the WDF coefficients. Custom computing parallel digital architectures are proposed for fast real-time updating of WDF coefficients as a function of beam angle and beam size. These coefficients are computed using algebraic approximation methods resulting in fast digital circuits. Digital designs are implemented on Xilinx Virtex-6 XC6VLX240T FPGA device and tested using on-chip hardware co-simulation. The designs are also synthesized, placed and routed for 45 nm standard cell ASIC technology using freePDK45 library to determine the area utilization, power consumption and the maximum speed of operation.

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Section: Fan Filterbanksmentioning

confidence: 81%

Section: Wave Digital Filtersmentioning

confidence: 99%

Section: Fan Filterbanksmentioning

confidence: 99%

“…We employ design equations in Bruton (2003) to implement bandpass filter H B P (n ct ). The fan-shape is obtained by scaling the beam size of each sub-band beam filter and band Fig.…”

Section: Fan Filterbanksmentioning

confidence: 99%

See 2 more Smart Citations

Fast FPGA-architecture for fan/beam-steering in wave-digital RF aperture arrays

Wijayaratna

Rajapaksha

Madanayake

et al. 2016

Multidim Syst Sign Process

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“…By referring to the 3D plane wave theory described earlier, a 3D beamformer can be realized in hardware by cascading two 2D beam filters directionally enhancing signals in (x, ct) and (y, ct) planes [34]. Thus, the transfer function of the 3D beam filter can be represented using 2D beam filters as follows:…”

Section: Cascaded Beam Filters For 3d Beamformersmentioning

confidence: 99%

Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform

2017

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Antenna array-based multi-dimensional infinite-impulse response (IIR) digital beamformers are employed in a multitude of radio frequency (RF) applications ranging from electronically-scanned radar, radio telescopes, long-range detection and target tracking. A method to design 3D IIR beam filters using 2D IIR beam filters is described. A cascaded 2D IIR beam filter architecture is proposed based on systolic array architecture as an alternative for an existing radar application. Differential-form transfer function and polyphase structures are employed in the design to gain an increase in the speed of operation to gigahertz range. The feasibility of practical implementation of a 4-phase polyphase 2D IIR beam filter is explored. A digital hardware prototype is designed, implemented and tested using a ROACH-2 Field Programmable Gate Array (FPGA) platform fitted with a Xilinx Virtex-6 SX475T FPGA chip and multi-input analog-to-digital converters (ADC) boards set to a maximum sampling rate of 960 MHz. The article describes a method to build a 3D IIR beamformer using polyphase structures. A comparison of technical specifications of an existing radar application based on phased-array and the proposed 3D IIR beamformer is also explained to illustrate the proposed method to be a better alternative for such applications.

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Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Sengupta

Madanayake

Gómez‐García

et al. 2016

Circuit Theory & Apps

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SUMMARYEmerging wide-band communications and spectrum-sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far-field beam width. Realizing existing phased-array technology on a digital scale is computationally intensive. Moreover, digitizing wide-band signals at Nyquist rate requires complex high-speed analog-to-digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low-complexity alternative proposed in this paper is the use of radio-frequency (RF) channelizers for spectrum division followed by sub-sampling of the RF sub-bands, which results in extensive reduction of the necessary ADC operative frequency. The RF-channelized array signals are directionally filtered using 2-D digital filterbanks. This mixed-domain RF/digital aperture array allows sub-sampling, without utilizing multi-rate 2-D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14-19 dB of rejection of wide-band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single-phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65-nm Xilinx field-programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area-time complexity, and dynamic power consumption for a 45-nm CMOS circuit operating at B DC = 1.1 V, are presented.

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Three-dimensional cone filter banks

Cited by 78 publications

References 6 publications

Fast FPGA-architecture for fan/beam-steering in wave-digital RF aperture arrays

Fast FPGA-architecture for fan/beam-steering in wave-digital RF aperture arrays

Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

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