Fast FPGA-architecture for fan/beam-steering in wave-digital RF aperture arrays

Abstract

A digital hardware architecture is proposed for computation of filter coefficients of 1st-and 2nd-order 2-D IIR beam/fan filters, which are capable of enhancement of RF plane-waves based on their direction of arrival, therefore having applications in steerable digital beamformers. Fan filters are designed using the WDF realization, which has superior sensitivity and stability properties since it is derived from the original passive continuousdomain prototype LC ladder network with impedance-matched resistive terminations. The orientation of the fan filter, which is determined by the look-direction of the radio beam, can be altered by the WDF coefficients. Custom computing parallel digital architectures are proposed for fast real-time updating of WDF coefficients as a function of beam angle and beam size. These coefficients are computed using algebraic approximation methods resulting in fast digital circuits. Digital designs are implemented on Xilinx Virtex-6 XC6VLX240T FPGA device and tested using on-chip hardware co-simulation. The designs are also synthesized, placed and routed for 45 nm standard cell ASIC technology using freePDK45 library to determine the area utilization, power consumption and the maximum speed of operation.