Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

Radojković, Petar; Cakarevic, Vladimir; Verdú, Javier; Pajuelo, Alex; Cazorla, Francisco J.; Nemirovsky, Mario; Valero, Mateo

doi:10.1109/tpds.2012.311

Cited by 25 publications

(17 citation statements)

References 37 publications

(44 reference statements)

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“…The performance of a given thread assignment can be predicted using a heuristic based on analysis of the application hardware requirements and properties of the target platform. Previous studies that address the process scheduling problem for multithreaded processors [20][45] [46][51] [52] present several systematic methods to predict the performance of workloads executed on multithreaded processors. Any such method may be used to predict the performance of the randomly-generated thread assignments.…”

Section: Sample Pruning and Sp-pot Algorithmmentioning

confidence: 99%

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Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Radojković

Carpenter

Moretó

et al. 2016

IEEE Trans. Comput.

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Abstract-The introduction of multicore/multithreaded processors, comprised of a large number of hardware contexts (virtual CPUs) that share resources at multiple levels, has made process scheduling, in particular assignment of running threads to available hardware contexts, an important aspect of system performance. Nevertheless, thread assignment of applications running on state-of-the art processors is an NP-complete problem. Over the years, numerous studies have proposed heuristic-based algorithms for thread assignment. Since the thread assignment problem is intractable, it is in general impossible to know the performance of the optimal assignment, so the room for improvement of a given algorithm is also unknown. It is therefore hard to decide whether to invest more effort and time to improve an algorithm that may already be close to optimal. In this paper, we present a statistical approach to the thread assignment problem. First, we present a method that predicts the performance of the optimal thread assignment, based on the observed performance of each thread assignment in a random sample. The method is based on Extreme Value Theory (EVT), a branch of statistics that analyses extreme deviations from the population mean. We also propose sample pruning, a method that significantly reduces the time required to apply the statistical method by reducing the number of candidate solutions that need to be measured. Finally, we show that, if no suitable heuristicbased algorithm is available, a sample of several thousand random thread assignments is enough to obtain, with high confidence, an assignment with performance close to optimal. The presented approach is architecture and application independent, and it can be used to address the thread assignment problem in various domains. It is especially well suited for systems in which the workload seldom changes. An example is network systems, which typically provide a constant set of services that are known in advance, with network applications performing a similar processing algorithm for each packet in the system. In this paper, we validate our methods with an industrial case study for a set of multithreaded network applications on an UltraSPARC T2 processor. This article is an extension of our previous work [44], which was published in

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Section: Sample Pruning and Sp-pot Algorithmmentioning

confidence: 99%

“…Step 1 of SP-POT algorithm, we predicted the performance of the thread assignments using the BlackBox scheduler [46]. The BlackBox scheduler is a model that predicts the performance of different thread assignments of applications running on multithreaded processors.…”

Section: Sp-pot Evaluationmentioning

confidence: 99%

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Radojković

Carpenter

Moretó

et al. 2016

IEEE Trans. Comput.

Self Cite

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“…Autopin itself does not detect the sharing pattern, it only verifies the IPC of several mappings fed to it and executes the application with the thread mapping that presented the highest IPC. The BlackBox scheduler [21], similar to Autopin, selects the best mapping by measuring the performance that each mapping obtained. When the number of threads is low, all possible thread mappings are evaluated.…”

Section: Related Workmentioning

confidence: 99%

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

Cruz

Diener

Pilla

et al. 2016

Euro-Par 2016: Parallel Processing

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Abstract. In modern shared-memory architectures, it is important to map threads and data in a way that increases the locality of their memory accesses, thereby improving performance and energy efficiency. Threads that access shared data should be mapped close to each other in the memory hierarchy, while the data they access should be mapped to their NUMA node, which is called sharing-aware mapping. In this paper, we propose SAMMU, which adds sharing-awareness to the memory management unit in current architectures. SAMMU analyzes the memory access behavior in hardware and provides information to the operating system so it can perform an online mapping of threads and data. In the evaluation with a wide range of parallel applications, performance was improved by up to 35.7% (13.1% on average).

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“…Autopin does not detect the sharing pattern, only verifies the IPC of several mappings fed to it and executes the application with the thread mapping that presented the highest IPC. Similarly, Blackbox [Radojković et al 2013] selects the best mapping by measuring the performance of 1000 random mappings. These methods seldom converge to an optimal mapping because the number of possible mappings is exponential in the number of threads.…”

Section: Thread Mapping Onlymentioning

confidence: 99%

Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures

Cruz

Diener

Pilla

et al. 2016

ACM Trans. Archit. Code Optim.

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The performance and energy efficiency of modern architectures depend on memory locality, which can be improved by thread and data mappings considering the memory access behavior of parallel applications. In this paper, we propose IPM, a mechanism that analyzes the memory access behavior using information about the time the entry of each page resides in the Translation Lookaside Buffer (TLB). It provides very accurate information with a very low overhead. We present experimental results with simulation and real machines, with average performance improvements of 13.7% and energy savings of 4.4%, which come from reductions in cache misses and interconnection traffic.

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Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

Cited by 25 publications

References 37 publications

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures

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