A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

Cruz, Eduardo H. M.; Diener, Matthias; Pilla, Laércio Lima; Navaux, Philippe O. A.

doi:10.1007/978-3-319-43659-3_36

Cited by 6 publications

(8 citation statements)

References 22 publications

(25 reference statements)

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“…To minimize remote memory access, memory access behaviors are detected, and pages are placed on the node with the most accesses to them. Some focus on sharing‐aware mapping, which maps threads accessing shared data to cores close to one another in the memory hierarchy and maps the data they accessed to their NUMA nodes. Some detect the memory access pattern for thread and data mapping on the hardware level, whereas some studies gather information from page faults or using a memory tracer tool.…”

Section: Technology Background and Related Workmentioning

confidence: 99%

“…Some focus on sharing‐aware mapping, which maps threads accessing shared data to cores close to one another in the memory hierarchy and maps the data they accessed to their NUMA nodes. Some detect the memory access pattern for thread and data mapping on the hardware level, whereas some studies gather information from page faults or using a memory tracer tool. Several studies proposed scheduling techniques, which arrange processes to run on cores in a specific way to avoid resource contention or use the load balancing view to reduce their demand for the same resources.…”

Section: Technology Background and Related Workmentioning

confidence: 99%

“…To reduce remote memory access and/or resource contention, existing studies use various strategies. Most of them focus on either the scheduling techniques and thread mapping strategies or memory placement and data mapping policies.…”

Section: Introductionmentioning

confidence: 99%

“…There are many related studies on the issues of thread mapping and data mapping to NUMA nodes, and their strategies substantially improve performance and energy efficiency. However, lacking the consideration of an OS kernel's internode load‐balancing activity will reduce the effect on performance improvement.…”

Section: Introductionmentioning

confidence: 99%

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Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Chiang

et al. 2019

Softw Pract Exp

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Although nonuniform memory access architecture provides better scalability for multicore systems, cores accessing memory on remote nodes take longer than those accessing on local nodes. Remote memory access accompanied by contention for internode interconnection degrades performance. Properly mapping threads to cores and data accessed to their nodes can substantially improve performance and energy efficiency. However, an operating system kernel's load-balancing activity may migrate threads across nodes, which thus messes up the thread mapping. Besides, subsequent data mapping behavior pays for the cost of page migration to reduce remote memory access. Once unsuitable threads are migrated, it is detrimental to system performance. This paper focuses on improving the kernel's internode load balancing on nonuniform memory access systems. We develop a memory-aware kernel mechanism and policies to reduce remote memory access incurred by internode thread migration. The Linux kernel's load balancing mechanism is modified to incorporate selection policies in the internode thread migration, and the kernel is modified to track the amount of memory used by each thread on each node. With this information, well-designed policies can then choose suitable threads for internode migration. The purpose is to avoid migrating a thread that might incur relatively more remote memory access and page migration. The experimental results show that with our mechanism and the proposed selection policies, the system performance is substantially increased when compared with the unmodified Linux kernel that does not consider memory usage and always migrates the first-fit thread in the runqueue that can be migrated to the target central processing unit.

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Section: Technology Background and Related Workmentioning

confidence: 99%

Section: Technology Background and Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Chiang

et al. 2019

Softw Pract Exp

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“…In addition to this, PAMS controls data movements between the main and the scratchpad memories. Sharing-Aware Memory Management Unit (SAMMU) [21] analyses the memory access behaviour on the hardware level. It also provides information to the operating system to perform an online thread-and data-mapping to increase the locality, thus improving performance.…”

Section: A Access Patternsmentioning

confidence: 99%

Survey of Memory Management Techniques for HPC and Cloud Computing

Pupykina

Agosta

2019

IEEE Access

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The emergence of new classes of HPC applications and usage models, such as real-time HPC and cloud HPC, coupled with the increasingly heterogeneous nature of HPC architectures, requires a renewed investigation of memory management solutions. Traditionally, memory is shared by an operating system using segmentation and paging techniques. At the same time, new classes of applications require Quality of Service (QoS) guarantees. As such, the typical practice of reserving a subset of the supercomputer to a single application becomes less attractive, leading to the exploration of cloud technologies. In this context, a viable scenario is that of multiple applications, with different QoS levels, coexisting on the same deeply heterogeneous HPC infrastructure and sharing resources. However, for this scenario to succeed in practice, resources, including memory, need to be allocated with a vision that includes both the application requirements and the current and future state of the overall system. In this survey, challenges of memory management in HPC and Cloud Computing, different memory management systems and optimisation techniques to increase memory utilisation are discussed in detail. INDEX TERMS Clouds, high performance computing, memory management, resource management. ANNA PUPYKINA received the higher education degree in data processing and control systems engineering from Samara State Aerospace University, Russia, in 2009. She is currently pursuing the Ph.D. degree with the Politecnico di Milano, under the supervision of Prof. G. Agosta. She was with Russian State Humanitarian University (RSUH), Togliatti, and also with the Department of Applied Mathematics and Informatics, Togliatti State University (TSU). Her main research interests include runtime management algorithms and programming model extensions for deeply heterogeneous systems. GIOVANNI AGOSTA received the Laurea degree in computer engineering and the Ph.D. degree in information technology from the Politecnico di Milano, Italy, in 2000 and 2004, respectively. He is currently a tenured Researcher. He has authored more than 80 articles in international journals, conferences, and workshops. His main research interest includes compiler technology. He was a recipient of four HiPEAC Awards and three Best Paper Awards. He has been involved in eight European funded projects, since 2010, holding workpackage and task leader responsibilities. He is a Full Member of the HiPEAC Network and the Organizer of two workshops colocated with the HiPEAC Conference.

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Mitigating execution unit contention in parallel applications using instruction‐aware mapping

Serpa

Cruz

Diener

et al. 2021

Concurrency and Computation

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Parallel applications running on simultaneous multithreading (SMT) processors naturally compete for execution units when their threads are mapped to the same core. This issue is further aggravated when such threads execute similar instructions that stress the same execution unit type, making their execution to behave very similarly as if the threads were running sequentially. This, in turn, will lead to performance degradation and underutilization of hardware resources. This work proposes a completely transparent framework (no modifications to the source code are necessary) that automatically maps threads of multiple parallel applications on SMT processors.The framework focuses on improving performance by mitigating the contention on execution units, considering each thread's instruction types, which are detected at runtime by our framework. Results show performance gains of 21% (geometric mean), compared to the native scheduler of the operating system.

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A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

Cited by 6 publications

References 22 publications

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Survey of Memory Management Techniques for HPC and Cloud Computing

Mitigating execution unit contention in parallel applications using instruction‐aware mapping

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