Third-generation architecture boosts speed and density of field-programmable gate arrays

Hsieh, Harry; Carter, W.S.; Ja, J.Y.; Cheung, Eric F. C.; Schreifels, S.; Erickson, Charles R.; Freidin, P.; Tinkey, L.; Kanazawa, R.

doi:10.1109/cicc.1990.124841

Cited by 94 publications

(52 citation statements)

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“…As result, numerous subsequent FPGAs (the Xilinx XC4000 family [103], Virtex series up to and including the Virtex 4 family, and Altera Flex, Apex, Cyclone, and Stratix I families) used basic clusters of 4-input lookup tables to implement logic. The input signal fanout leveraged in the Xilinx XC3000 architecture is achieved by distributing cluster inputs to multiple LUT-based basic logic elements.…”

Section: Commercial Logic Blocksmentioning

confidence: 99%

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FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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Section: Commercial Logic Blocksmentioning

confidence: 99%

“…The Xilinx XC4000 series FPGAs [103], and all subsequent Xilinx FPGAs provide the ability to turn LUTs in the soft fabric into small memories. These memories can be connected together to form larger memories.…”

Section: Soft Fabric Heterogeneitymentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

317

109

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“…In the regular segmented architecture, all connectable wires form a routing domain, and all wires which belong to a common domain have the same length. This is a segmentation style similar to the one adopted in the popular Xc4000 chips [2,10].…”

Section: Regular Segmented Fpga Architecturementioning

confidence: 99%

“…In this paper we address the architectural routability optimization aspect for the regular segmentation type FPGAs. In particular we focus on routing architectures whose resources can be partitioned into disjoint domains [2,5,6,8,10] with each domain composed of wire segments of the same length. In the past, routing optimization has been mostly addressed as a resource contention problem, here we show that there is still an overlooked pin topology issue for regular segmented architectures.…”

Section: Malgorzata Marek-sadowska + + Department Of Electrical and Cmentioning

confidence: 99%

Routing on regular segmented 2-D FPGAs

Marek-Sadowska²

1995

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 With EDA Technofair

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“…I N the symmetrical-array FPGA architecture [1], [8], [20], routing resources consist of horizontal and vertical channels and their intersecting areas. The layout in such an architecture is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Algorithms for an FPGA switch module routing problem with application to global routing

Thakur¹,

Chang²,

Wong³

et al. 1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We consider a switch module routing problem for symmetrical-array field-programmable gate arrays (FPGA's). This problem was first introduced in [21]. They used it to evaluate the routability properties of switch modules which they proposed. Only an approximation algorithm for the problem was proposed by them. We give an optimal algorithm for the problem based on integer linear programming (ILP). Experiments show that this formulation leads to fast and efficient solutions to practical-sized problems. We then propose a precomputation that eliminates the need to use ILP on-line. We also identify special cases of this problem that reduce to problems for whom efficient algorithms are known. Thus, the switch module routing problem can be solved in polynomial time for these special cases. Using our solution to the switch module routing problem, we propose a new metric to estimate the congestion in each switch module in the FPGA. We demonstrate the use of this metric in a global router. A comparison with a global router guided by the density of the routing channels shows that our metric leads to far superior global and detailed routing solutions.

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Third-generation architecture boosts speed and density of field-programmable gate arrays

Cited by 94 publications

References 1 publication

FPGA Architecture: Survey and Challenges

FPGA Architecture: Survey and Challenges

Routing on regular segmented 2-D FPGAs

Algorithms for an FPGA switch module routing problem with application to global routing

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