Thin Film Transistors with Graded SiN x Gate Dielectrics

Abstract

This paper presents results on thin film transistors with graded SiN~ gate dielectrics. All SiN= and a-Si:H films were prepared using 250~ plasma-enhanced chemical vapor deposition processes. Device characteristics such as mobility, threshold voltage, subthreshold slope, and on/off current are discussed. The graded gate dielectric thin film transistor (TFT) may have better or worse device performance compared with the single gate dielectric TFT, depending on the interface dielectric deposition condition. The interface SiN= deposition process influences the intensity density of states between the a-Si:H layer and the gate SiN~ layer as well as the states between the first and the second (interface) SiN= layers. The stress mismatch between the first and the second SiN= layers also has a profound influence on TFT characteristics. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 134.129.182.74 Downloaded on 2015-06-05 to IP ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 134.129.182.74 Downloaded on 2015-06-05 to IP ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 134.129.182.74 Downloaded on 2015-06-05 to IP

The Effect of Interface States on Single-Walled Carbon Nanotube Transistors

“…25 PECVD deposited SiN x at low temperature (225 • C) with increasing NH 3 /SiH 4 ratio will increase the amount of fixed charges (Si≡N + ) which can n-dope the semiconducting (6,5) SWCNT 15 and simultaneously form charge traps. [22][23][24][25] With weak n-doping, the depletion region between conduction band and metal electrode will not be narrow enough for electron to tunnel through (Figure 5A). 38 This will result in the injection barrier, as evidenced in Figure 3D (device 20150723A5) in which the nonlinear I-V curves were observed at low V DS .…”

“…Silicon nitride has widely used as the dielectrics in amorphous silicon thin film transistors, crucially dependent on the interface and bulk properties of gate dielectrics. [22][23][24] The energy levels of defect states in amorphous silicon nitride are used to identify the nature of trap states responsible for charge trapping. 25 The interface provides a channel for tailoring the free charge and trapped charge by gate potential.…”

Combinatorial solid state materials science and technology

“…We have also developed a combinatorial PECVD system for a-Si:H based alloys and devices which are critical to the promising low-cost large area microelectronics [19,20]. In this technique, typically, a 'contact' mask with predefined pixel matrix is placed over the substrate/s of interest and a sequence of different depositions is carried out along x-axis of the substrate by moving a 'slit' mask over the 'contact' mask exposing one pixel row to the plasma at a time.…”

High-quality SiNx thin-film growth at 300 °C using atomic layer deposition with hollow-cathode plasma

“…Silicon nitride (SiN x ) is one of the most widely used thin films in semiconductor device integration processes, as gate spacers, gate dielectrics, charge trapping layers, hard etch masks, and passivation layers. [1][2][3][4][5][6][7][8][9][10][11][12] Meanwhile, three-dimensional structured devices such as fin field-effect transistors (FinFETs), gate-all-around FETs (GAA FETs), and three-dimensional NAND flash devices, which were recently introduced to improve their performances and integration efficiency, require an excellent step coverage in a high aspect-ratio structure. [13][14][15] Therefore, the atomic layer deposition (ALD) of SiN x films has been studied extensively, because the ALD process, which is based on a self-limiting surface reaction, exhibits outstanding thickness uniformity and step coverage.…”