Thin film encapsulation technology for harms using sacrificial CF-polymer

Reuter, Danny; Bertz, A.; Nowack, M.; Geßner, Thomas

doi:10.1016/j.sna.2007.11.002

Cited by 20 publications

(20 citation statements)

References 11 publications

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“…Moreover, some thin film packages not only play a role in protection of the device, but also are a functional part of the whole systems [1]. For example, thin film vacuum packages are crucial parts of many MEMS to reduce air damping [2]. Normally, the vacuum inside the package is realized by sealing the packaging in a vacuum environment, for instance, by vacuum thin film deposition.…”

mentioning

confidence: 99%

Outgassing of materials used for thin film vacuum packages

Goosen

Beek

et al. 2009

2009 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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In this paper, outgassing of the thin film vacuum package is analyzed by integrated MEMS (Microelectromechanical system) resonator and RBS (Rutherford backscattering spectroscopy). Outgassing behavior of different thin film packaging materials is studied by exodiffusion experiments. It is demonstrated that a high temperature pre anneal will greatly reduce the outgassing but can not eliminate it. Thin film vacuum packagingThin film packaging technology is essential for miniaturization and high level integration of semiconductor components. It allows for the encapsulation of MEMS or ICs (Integrated Circuits) at the wafer level using micromachining technology before the standard IC packaging process [1].The typical steps for thin film packaging are illustrated in Fig. 1. The packaging process normally starts after the MEMS is fabricated and can be easily integrated into the back end of the MEMS process. The critical steps include sacrificial layer deposition, first thin film deposition, etching holes on the thin film, releasing the sacrificial layer through the etched holes, and sealing the package by another thin film layer. Fig. 1. A conceptual process flow of creating a thin film package around a MEMS device.The thin film package protects the free standing micro structures on the wafer and isolates the contamination in the environment. Compared with another wafer level packaging technique, the bonded package, it greatly reduces the size and cost of the package, and simplifies the process. Moreover, some thin film packages not only play a role in protection of the device, but also are a functional part of the whole systems [1]. For example, thin film vacuum packages are crucial parts of many MEMS to reduce air damping [2]. Normally, the vacuum inside the package is realized by sealing the packaging in a vacuum environment, for instance, by vacuum thin film deposition.The successful packaging of such MEMS by thin film technology relies on the long-term stability of the thin film material. Outgassing of the thin film materialsVapor deposition technologies like PECVD (Plasma Enhanced Chemical Vapor Deposition) and LPCVD (Low Pressure Chemical Vapor Deposition) are typical ways to fabricate thin films [3]. Outgassing is one of the biggest concerns for the thin film vacuum package, since some gas molecules, like Hydrogen, may be incorporated inside the thin films during the deposition process [3] and may outgas under certain conditions. When outgassing happens, the freed gas will enter the inside of the thin film package and spoil the vacuum. This may happen after a long period of time or due to environmental changes such as thermal loading.Thermal loading is likely to happen in the MEMS process. For instance, a PECVD silicon nitride deposition with a thermal loading of about 300ºC to 450ºC may be used for the final anti scratch step for the wafers. Moreover, the temperature of standard IC packaging, which is often carried out after the thin film packaging, may reach several hundred degrees Celsius. The vacuum thin fil...

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mentioning

confidence: 99%

Outgassing of materials used for thin film vacuum packages

Goosen

Beek

et al. 2009

2009 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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“…For instance, in case of a 0-level vacuum sealed cavity, the cap (either thin film or chip cap) must sustain one atmosphere (10 5 Pa) of differential hydrostatic pressure without collapsing or significant deformation [20][21][22]. The hydrostatic strength or perhaps better, the flexural stiffness of a membrane or (composite) capping layer is determined by a complex interplay between the geometry and thickness of the membrane, the residual stress in the membrane layer(s), the Young's modulus of the membrane material(s), and the clamping conditions of the membrane.…”

Section: Strength and (Thermo)mechanical Loadingmentioning

confidence: 99%

“…If the thermally induced stress is greater than the maximum allowable stress in any of the materials involved, the package or the device fail, either as a result of delamination (or de-adhesion) or excessive yielding (of the MEMS material) or even destructive fracture. Especially stress concentrations may lead to destructive failure [20][21][22].…”

Section: Strength and (Thermo)mechanical Loadingmentioning

confidence: 99%

MEMS packaging and reliability: An undividable couple

Tilmans

Coster

Hélin

et al. 2012

Microelectronics Reliability

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“…also require a stable and controlled environment, like vacuum for instance, for reliable operation. These challenging demands are usually fulfilled by means of packaging MEMS devices on the wafer-level using either wafer bonding [1,2] or thin-film chip-scale encapsulation [1][2][3][4][5][6], also known as zero-level packaging. Typical requirements for wafer-level MEMS packaging are low cost processing, CMOS compatibility (in terms of materials employed, process development and device compatibility), hermeticity, robustness, stability, good sealing characteristics and an ability to withstand harsh environments.…”

Section: Introductionmentioning

confidence: 99%

Robust Wafer-Level Thin-Film Encapsulation of Microstructures using Low Stress PECVD Silicon Carbide

Rajaraman¹,

Pakula²,

Pham

et al. 2009

2009 IEEE 22nd International Conference on Micro Electro Mechanical Systems

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This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface-and thin-SOI microstructures that included microcavities, RF switches and various accelerometers. Advantages of our technique are its versatility, smaller footprint, reduced chip thickness and process complexity, post-CMOS batch processing capability and added functionality due to the possibility of integrating additional electrodes for MEMS. Besides fabrication details, this work also discusses related design aspects for large-area MEMS and demonstrates the encapsulation results. Successfully encapsulation of device geometries as large as 955x827.m2 has been achieved.

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Thin film encapsulation technology for harms using sacrificial CF-polymer

Cited by 20 publications

References 11 publications

Outgassing of materials used for thin film vacuum packages

Outgassing of materials used for thin film vacuum packages

MEMS packaging and reliability: An undividable couple

Robust Wafer-Level Thin-Film Encapsulation of Microstructures using Low Stress PECVD Silicon Carbide

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