Thin film decoupling capacitors: a high frequency performance analysis

Schaper, L.W.; Chen, K.Y.; Brown, W.D.; Ang, Simon S.; Naseem, Hameed A.

doi:10.1109/ectc.1999.776283

Cited by 9 publications

(2 citation statements)

References 11 publications

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“…We generated our models exclusively from the nominal physical parameters shown in Table II. Our models took into account the location of the probes and replicated the series capacitor structure reported in [7]. The impedance vs. frequency of our models, together with that of the RLC parameters extracted from the measurements by the authors of [7], (essentially identical to the actual measurement results) is shown in Figs.…”

Section: Electrical Measurements/model Verificationmentioning

confidence: 90%

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Modeling and simulation of integrated capacitors for high frequency chip power decoupling

Diaz-Alvarez

Krusius

Kroeger³

2000

IEEE Trans. Comp. Packag. Technol.

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Power and ground decoupling is typically accomplished using a hierarchy of discrete capacitors spread throughout the power distribution network. Many of the limitations of discrete decoupling capacitors can be overcome with integrated capacitors. A modeling approach for integrated capacitors based on the partial-element-equivalent-circuit (PEEC) formulation is presented. This approach has been applied to 3M C-ply, a flexible planar integrated capacitor technology that can be laminated into multilayer substrates, such as printed wiring boards. The decoupling capability of 3M C-Ply technology for chip power distribution has been compared with conventional surface-mount technology (SMT). Index Terms-Chipdecoupling circuit simulation, chip power decoupling, integrated capacitor in substrate, PEEC modeling. 1521-3331/00$10.00 © 2000 IEEE Enrique Diaz-Alvarez received the B.S. degree (with honors) in electrical engineering from The Ohio State University, Columbus, in 1994 and the Ph.D. degree from Cornell University, Ithaca, NY, in 2000.His research interests are modeling and simulation of electronic packaging and mixed-signal systems, with particular view to integrated capacitor modeling and the development of new signal packaging architectures providing high degree of electrical isolation between RF, analog, and digital partitions. J. Peter Krusius (M'80-SM'87) received the Ph.D. degree from Helsinki

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Section: Electrical Measurements/model Verificationmentioning

confidence: 90%

“…[7], and then comparing the predicted frequency response characteristics with measured data from this reference. We generated our models exclusively from the nominal physical parameters shown in Table II.…”

Section: Electrical Measurements/model Verificationmentioning

confidence: 99%