Power and ground decoupling is typically accomplished using a hierarchy of discrete capacitors spread throughout the power distribution network. Many of the limitations of discrete decoupling capacitors can be overcome with integrated capacitors. A modeling approach for integrated capacitors based on the partial-element-equivalent-circuit (PEEC) formulation is presented. This approach has been applied to 3M C-ply, a flexible planar integrated capacitor technology that can be laminated into multilayer substrates, such as printed wiring boards. The decoupling capability of 3M C-Ply technology for chip power distribution has been compared with conventional surface-mount technology (SMT).
Index Terms-Chipdecoupling circuit simulation, chip power decoupling, integrated capacitor in substrate, PEEC modeling. 1521-3331/00$10.00 © 2000 IEEE Enrique Diaz-Alvarez received the B.S. degree (with honors) in electrical engineering from The Ohio State University, Columbus, in 1994 and the Ph.D. degree from Cornell University, Ithaca, NY, in 2000.His research interests are modeling and simulation of electronic packaging and mixed-signal systems, with particular view to integrated capacitor modeling and the development of new signal packaging architectures providing high degree of electrical isolation between RF, analog, and digital partitions. J. Peter Krusius (M'80-SM'87) received the Ph.D. degree from Helsinki