Thin Epitaxial Silicon Foils Using Porous-Silicon-Based Lift-Off for Photovoltaic Application

Abstract

In order to reduce the material cost for silicon solar cells, several research groups are investigating methods to minimize the silicon consumption for making monocrystalline silicon wafers. One promising approach is deposition of an epitaxial layer on porous silicon, followed by detachment of the layer. This contribution discusses improvements in the epitaxial wafer fabrication by optimization of the porosification process. The introduction of a layered porous silicon structure allows to independently improve both epitaxial layer quality and detachment yield. In this way, we have managed to obtain 100µm thick silicon wafers with effective lifetimes up to 1.3ms, and 40µm thick wafers with effective lifetimes up to 700µs. We will also review the current status of the process development for solar cells made on thin wafers. Two approaches are presented. In the first approach, heterojunction solar cells are fabricated on freestanding epitaxial wafers of 40µm thickness. In the second approach, high efficiency (21%) heterojunction back-contacted cells are fabricated on wafers that are bonded to a glass superstrate. Challenges for device processing and limitations in cell performance are discussed.

Liquid phase crystallized silicon – A holistic absorber quality assessment

“…Many approaches are being pursued to bring down material consumption of Si solar cells using the wafering process by alternative fabrication techniques. These alternatives include classical thin-film technologies like amorphous (a-Si) or microcrystalline (µ-c-Si) Si [1][2][3], top-down approaches like epitaxial lift-off techniques [4,5] or the liquid phase crystallization (LPC) technology [6]. All of them offer the potential to save material cost while having the advantage to rely on a vast existing knowledge on (crystalline) Si photovoltaics.…”

“…The technology represents thus a hybrid between wafers and classical bottom-up thin-film technologies. Contrary to that, the elaborate top-down epitaxial lift-off technique uses a high quality mono-crystalline and reusable parent wafer from which absorbers are lifted off and bonded to a substrate [4,5]. Efficiencies of up to 20.6 % were presented on 35 µm Si [10].…”

Silicon heterojunction interdigitated back-contact solar cells bonded to glass with efficiency >21%

“…However, such thin wafers are much more mechanically fragile than standard ~180-µm-thick wafers, which are widely used today on production lines [1]. To reduce wafer breakage and achieve high industrial production yield, proper industrial handling techniques of thin wafers are essential [7]. One possible approach is to mechanically support the thin wafer with rigid carriers during wafer transport and cell processing [8][9][10][11][12].…”

Impact of PECVD-prepared interfacial Si and SiGe layers on epitaxial Si films grown by PECVD (200 °C) and APCVD (1130 °C)

“…For example, wafer surface cleaning methods such as HF-based wet cleaning [18,19] and plasma-based dry cleaning with SiF 4 [20,21], Ar [22], H 2 [23,24]. Moreover a wide variety of surface preparation methods has been studied, such as (i) epitaxial Si layer on Si substrate by a bilayer interface with hydrogen incorporation [25]; (ii) epitaxial Si growth on HF-prepared porous Si surface [26]; (iii) Ge epitaxial layers on Si substrate with an Fe 3 Si insertion layer [27]; (iv) GaAs substrate with Ga-rich surface for Ge epitaxy [28]; (v) Ge buffer layers on Si substrate for epitaxial III-V layer [29]; (vi) SiGe graded buffer layer for SiGe growth on Si [30]; (vii) lapped and chemically polished Si substrate for epitaxial Si layer [31]; (viii) strained Si layer grown by He ion implantation into Si/SiGe heterostructures [32]; and (ix) heteroepitaxial growth of GaSb on Si [33] or Ge on Si [34] with the help of nanodot crystals contacted through nanowindows in an interfacial SiO 2 layer on Si substrates.…”