Thickness dependence of the resistivity of platinum-group metal thin films

Dutta, Shibesh; Sankaran, Kiroubanand; Moors, Kristof; Pourtois, Geoffrey; Elshocht, Sven Van; Bömmels, J.; Vandervorst, Wilfried; Tőkei, Zsolt; Adelmann, Christoph

doi:10.1063/1.4992089

Cited by 153 publications

(139 citation statements)

References 77 publications

(129 reference statements)

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“…Figure 1 shows a schematic of the Ta\TaO x \Pt cross-point memristor integration on the CMOS circuit, with detailed back-end-of-the-line (BEOL) process described in the Experimental Section. [34] We fabricated memristors with four different cross-point sizes on the same chip to minimize the variability caused by fabrication, such as film composition, layer thickness, and surface conditions. TaO x is chosen as switching material owing to its favorable memristive switching behavior and CMOS process compatibility.…”

Section: Memristor and Cmos Integrationmentioning

confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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in computing accelerators compared to high density storage-class memory, it is frequently important in computing applications to program multiple bits of information within every device by achieving many distinct conductance levels, while keeping the operating currents lower especially at the high conductance states. Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy. For example, in analog matrix-vector multiplication, voltage drops across metal interconnect lines cause computational errors and, therefore, the memristor array size must be limited. [6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. This further benefits the energy and area efficiency by amortizing the costs of anolog to digital converters (ADC) required in the circuit. [4] However, existing demonstrations have a narrow dynamic range and achieving multiple low conductance levels is challenging. A larger ratio between the high and low conductances (on/off ratio) helps in achieving more distinct programmable low conductance levels. In addition, memristors are required to be integrated with CMOS circuits in many such applications. For instance, a 1-transistor-1-memristor (1T1M) combination provides in situ current compliance through gate voltage modulation so that the memristor can be programmed in an analog manner. [12,16,25] This brings another challenge: compatibility of memristor and CMOS. This includes not only material and fabrication compatibility, but also CMOS performance meeting the memristor operating requirements as both continue size scaling. Thus, it is essential to demonstrate all the aforementioned properties in nanometer-scale memristors repeatedly and reproducibly.Among various forms of memristors, oxide memristors outperform others by possessing the advantages of lower programming and computing energy, favorable scaling in cell size, [10,11,30] and CMOS-compatibility in materials and fabrication. Recently, many reports demonstrated enouraging results using multiple-bits in HfO x , TaO x , and other oxide memristors for neuromorphic computing applications, [23][24][25]31,32] making these highly promising if CMOS-integrated nanoscale devices can be demonstrated wtih wide dynamic range and promising yield numbers.Using memristors, such as oxide and phase change resistive switches, as tunable resistors to construct analog computing hardware accelerators is gaining keen attention. Such accelerators have demonstrated the potential to significantly outperform digital computers in highly relevant applications such as machine learning and image processing. However, improvements in device-level performance of memristors, including reducing power consumption and high current-induced metal migration in interconnects, need continued developments. Nanoscaling and complementary metal-oxide semiconductor (CMOS) integration are also of significant ...

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Section: Memristor and Cmos Integrationmentioning

confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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“…8 the result of the Pt(10 nm)/Cu(10 nm) sample. The 100 mA current resulted in a current density in the Pt layer of j = 2.6 × 10 6 A/cm 2 after accounting for the shunting through Cu, using thin film resistivity values [33].…”

Section: Pt/cumentioning

confidence: 99%

X-ray spectroscopy of current-induced spin-orbit torques and spin accumulation in Pt/3d -transition-metal bilayers

et al. 2019

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An electric current flowing in Pt, a material with strong spin-orbit coupling, leads to spins accumulating at the interfaces by virtue of the spin Hall effect and interfacial charge-spin conversion. We measure the influence of these interfacial magnetic moments onto adjacent 3d transition metal layers by x-ray absorption spectroscopy and x-ray magnetic circular dichroism in a quantitative and element-selective way, with sensitivity below 10 −5 µB per atom. In Pt(6 nm)/Co(2.5 nm), the accumulated spins cause a deviation of the Co magnetization direction, which corresponds to an effective spin-Hall angle of 0.08. The spin and orbital magnetic moments of Co are affected in equal proportion by the absorption of the spin current, showing that the transfer of orbital momentum from the recently predicted orbital Hall effect is either below our detection limit, or not directed to the 3d states of Co. For Pt/NM (NM = Ti, Cr, Cu), we find upper limits for the amount of injected spins corresponding to about 3 × 10 −6 µB per atom.

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“…Figure 2 show the calculated TCR at 300 K for Ru (λ = 6.6 nm and ρ 0 = 7.6 Θ D = 420 K, µΩcm at 300 K, g = h, R = 0.5). As for Cu, the experimentally determined R value for Ru is used [48]. In contrast to Cu, p has no influence on the TCR for the chosen set of parameters.…”

Section: Marom and Eizenberg Have Derived Analytical Expressions Of Tmentioning

confidence: 99%

On the extraction of resistivity and area of nanoscale interconnect lines by temperature-dependent resistance measurements

Adelmann

2019

Solid-State Electronics

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Several issues concerning the applicability of the temperature coefficient of the resistivity (TCR) method to scaled interconnect lines are discussed. The central approximation of the TCR method, i.e. the substitution of the interconnect wire TCR by the bulk TCR becomes doubtful when the resistivity of the conductor metal is strongly increased by finite size effects. Semiclassical calculations for thin films show that the TCR deviates from bulk values when the surface roughness scattering contribution to the total resistivity becomes significant with respect to grain boundary scattering, an effect that might become even more important in nanowires due to their larger surface-to-volume ration. In addition, the TCR method is redeveloped to account for line width roughness. It is shown that for rough wires, the TCR method yields the harmonic average of the cross-sectional area as well as, to first order, the accurate value of the resistivity at the extracted area. Finally, the effect of a conductive barrier or liner layer on the TCR method is discussed. It is shown that the liner or barrier parallel conductance can only be neglected when it is lower than about 5 to 10% of the total conductance. It is furthermore shown that neglecting the liner/barrier parallel conductance leads mainly to an overestimation of the cross-sectional area of the center conductor whereas its resistivity is less affected.

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Thickness dependence of the resistivity of platinum-group metal thin films

Cited by 153 publications

References 77 publications

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

X-ray spectroscopy of current-induced spin-orbit torques and spin accumulation in Pt/3d -transition-metal bilayers

On the extraction of resistivity and area of nanoscale interconnect lines by temperature-dependent resistance measurements

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