“…Such microstructures include CMOS polysilicon or aluminum layers sandwiched between the CMOS dielectric layers, ie, the thermal silicon dioxide, the silicon dioxides produced by chemical vapor deposition (CVD), and the silicon dioxide-nitride passivation. The preferred etchant is EDP (ethylenediamine pyrocatechol) optimized with respect to the removal of substrate silicon while conserving the passivation and the metal pads of the CMOS process [5,6]. By design, the passivation layer serves as an etching mask and no further mask is required.…”