Thermodynamic considerations of junction capacitance

Toward Ultrafast Tuning and Triggering Single-Photon Electroluminescence of Color Centers in Silicon Carbide

“…Therefore, the capacitance per unit device width C n-p between the n-type and p-type contacts of the forward-biased GT-SPED is rather high due to the charge carrier diffusion capacitance. 19 Using the distributions obtained in the numerical simulations of the electron and hole transport in the GT-SPED and the thermodynamic definition of capacitance 37 given by…”

“…Therefore, the capacitance per unit device width C n‑p between the n-type and p-type contacts of the forward-biased GT-SPED is rather high due to the charge carrier diffusion capacitance . Using the distributions obtained in the numerical simulations of the electron and hole transport in the GT-SPED and the thermodynamic definition of capacitance given by where V is either the gate or bias voltage, E ( x , y , V ), n ( x , y , V ), and p ( x , y , V ) are the electric field, electron density, and hole density distributions, and n i is the intrinsic electron density in 4H-SiC, we estimate C p‑n to be 3 nF/cm at V bias = 2.77 V ( J = 30 A/cm 2 ). The resistance in the transient process can be estimated from the current–voltage characteristics V bias ( I ) as R p‑n = d V bias /d I = 10 Ωcm, which gives a characteristic time of R p‑n C p‑n = 30 ns.…”

“…Therefore, the capacitance per unit device width C n-p between the n-type and p-type contacts of the forward-biased GT-SPED is rather high due to the charge carrier diffusion capacitance. 18) Using the thermodynamic definition of capacitance 29) and the distributions obtained in the numerical simulations of the electron and hole transport in the steady state, we find C p-n to be about 3 nF/cm at V bias =2.77 V. The resistance in the transient process can be estimated from the current-voltage characteristics V bias (I) as (e) and 1(f)). Therefore, these electrons stream to the potential well virtually without resistance, i.e., the corresponding resistance R gate is lower than R p-n .…”

Semiconductor measurement technology

“…How can the seemingly conflicting answers [17,18] to these claims be resolved? 3. A method has been suggested for theoretically testing the validity of the Schottky equations [15,16] What are the proper definitions [19,20,21] [23][24][25][26][27][28].…”