Thermo-mechanical Analysis and Fatigue Life Prediction for Integrated Circuits (ICs)

Oukaira, Aziz; Touati, Djallel Eddine; Hassan, Ahmad; Ali, Mohamed; Savaria, Yvon; Lakhssassi, Ahmed

doi:10.1109/mwscas47672.2021.9531747

Cited by 8 publications

(2 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the thermal conductivity of this layer is often disregarded due to its narrowness and the focus on its electrical conductance within the bonding lane [35,36]. However, the junction layer, despite its narrowness, possesses significant heat conductivity [37,38], making it one of the crucial factors affecting heat distribution. Table 2 lists the parameters used in the model.…”

Section: Heat Analysis Of Sips Based On Cclcmentioning

confidence: 99%

Advanced Thermal Control Using Chip Cooling Laminate Chip (CCLC) with Finite Element Method for System-in-Package (SiP) Technology

et al. 2023

Self Cite

View full text Add to dashboard Cite

This paper introduces a novel approach to address thermal management challenges in system-in-package (SiP) technology, which is a significant concern in various advanced technologies. The main objective is to assess the electrical and thermal performance of the SiP model by utilizing Chip Cooling Laminate Chip (CCLC) technology. To achieve this, we employed finite element method (FEM) analysis using COMSOL Multiphysics® and MATLAB® to compare the results of electrical and thermal SiP models with and without CCLC technology. The numerical simulations revealed that, as opposed to the traditional model, the temperature variation decreased significantly with a uniform temperature distribution when employing the CCLC technology. Additionally, the thermal conduction performance of the packaging system using CCLC demonstrated remarkable reliability and resolution with cost-effective micro-devices, particularly in micro-medicine applications. The analysis of the electrical and thermal models reported a maximum error between them of 1.15 ∘C.

show abstract

Section: Heat Analysis Of Sips Based On Cclcmentioning

confidence: 99%

Advanced Thermal Control Using Chip Cooling Laminate Chip (CCLC) with Finite Element Method for System-in-Package (SiP) Technology

et al. 2023

Self Cite

View full text Add to dashboard Cite

show abstract

“…Due to the evolution of integration technologies with their ever-increasing power densities and clock frequencies, the performance, lifetime, and reliability of systems-on-chips (SoCs) have become more severely constrained by thermal issues than ever before. Failure mechanisms such as electromigration and thermomechanical stress, notably caused by the increased leakage power consumption [1][2][3], can increase the cooling cost and give rise to timing failures due to interconnect delays [4][5][6][7]. To tackle the thermal challenges associated with SoC implementation, designers commonly use thermal-aware floorplanning techniques to reduce thermal peaks and equally distribute temperature across a die.…”

Section: Introductionmentioning

confidence: 99%

Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors

et al. 2023

Self Cite

View full text Add to dashboard Cite

The reliability and lifetime of systems-on-chip (SoCs) are being seriously threatened by thermal issues. In modern SoCs, dynamic thermal management (DTM) uses the thermal data captured by thermal sensors to constantly track the hot spots and thermal peak locations in real time. Estimating peak temperatures and the location of these peaks can play a crucial role for DTM systems, as temperature underestimation can cause SoCs to fail and have shortened lifetime. In this paper, a novel sensor allocation algorithm (called thermal gradient tracker, TGT), based on the recursive elimination of regions that likely do not contain any thermal peaks, is proposed for determining regions that potentially contain thermal peaks. Then, based on an empirical source temperature detection technique called GDS (gradient direction sensor), a hybrid algorithm for detecting the position and temperature of thermal peaks is also proposed to increase the accuracy of temperature sensing while trying to keep the number of thermal sensors to a minimum. The essential parameters, H and R, of the GDS technique are determined using an automated search algorithm based on simulated annealing. The proposed algorithm has been applied in a system-on-chip (SoC) in which four heat sources are present, and for temperatures ranging between 45 °C and 115 °C, in a chip area equal to 25 mm2. The simulation results show that our proposed sensor allocation scheme can detect on-chip peaks with a maximum error of 1.48 °C and an average maximum error of 0.49 °C by using 15 thermal sensors.

show abstract

Analytical and Numerical Modeling of the Thermal Performance of 3D System-in-Package (SiP)

Benelhaouare,

Oumlaz,

Oukaira

et al. 2023

2023 International Conference on Electrical, Computer and Energy Technologies (ICECET)

View full text Add to dashboard Cite

Thermo-mechanical Analysis and Fatigue Life Prediction for Integrated Circuits (ICs)

Cited by 8 publications

References 15 publications

Advanced Thermal Control Using Chip Cooling Laminate Chip (CCLC) with Finite Element Method for System-in-Package (SiP) Technology

Advanced Thermal Control Using Chip Cooling Laminate Chip (CCLC) with Finite Element Method for System-in-Package (SiP) Technology

Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors

Analytical and Numerical Modeling of the Thermal Performance of 3D System-in-Package (SiP)

Contact Info

Product

Resources

About