With the decreasing design rules of large-scale integrated (LSI) device manufacturing, Czochralski (CZ) silicon wafers must be free of defects in the active layer in order to maintain device performance. In addition, CZ silicon wafers must include oxide precipitates in the bulk region for internal gettering (IG) of metallic contamination. It has been reported that such wafers can be produced by hydrogen annealing at high temperatures. 1-3 Hydrogen-annealed CZ silicon (H 2 -annealed) wafers do not have grown-in defects, such as crystal-originated particles at the surface. In addition, the density of oxide precipitates in the bulk region can be controlled by adjusting the temperature ramp-up rate during hydrogen annealing. 3 It is well known that the existence of oxide precipitates degrades the mechanical strength of CZ wafers in device processes. 4-15 That is, the thermal stress in the wafer causes slip dislocation generation by oxide precipitates. Since the thermal stress should increase with an increase in the diameter of wafers, the problem of slip dislocation generation becomes more serious. As the oxide precipitates in H 2 -annealed wafers grow during device fabrication, the mechanical strength of H 2 -annealed wafers during device processes should be investigated to avoid slip generation. However, few investigations of the mechanical strength of H 2 -annealed wafers in device processes have been reported.In this work the mechanical strength of H 2 -annealed wafers is investigated with emphasis on slip generation by oxide precipitates using thermal simulation of a low-temperature process (low-temperature simulation) or a high-temperature process (high-temperature simulation).Experimental The samples used were p-type (boron-doped, 1-10 ⍀ cm), 6 in., CZ-Si <100> wafers. Interstitial oxygen concentration was determined at room temperature by Fourier transform infrared spectroscopy (FTIR). The oxygen concentration of the as-grown wafers was (13.5 Ϯ 0.2) ϫ 10 17 atoms/cm 3 with a 1107 cm Ϫ1 absorption line and a conversion factor of 4.81 ϫ 10 17 atoms/cm 2 . Hydrogen annealing was performed on these wafers at 1200ЊC for 1 h. After hydrogen annealing two types of annealing were performed to simulate actual device processes: a low-temperature simulation with a maximum temperature at 950ЊC for 1 h and a high-temperature simulation with a maximum temperature at 1190ЊC for 6.7 h. In these thermal simulations, the introduction of slip dislocations due to thermal stress was completely avoided by slowly heating and cooling the wafers.Thermal stress was applied in an N 2 ambient to these simulated wafers as follows. The wafers were set on a boat with 3.5 mm spacing and inserted and withdrawn from a horizontal tube at a rate of 15 cm/min. Operating temperature was 1000ЊC and the holding time at this temperature was 30 min. After the thermal stress test, generated slip dislocations were investigated using X-ray topography (XRT) and transmission electron microscopy (TEM) observations. TEM samples were prepared by mechanical g...