Thermal Stress Measurement in Silicon Chips Encapsulated in IC Plastic Packages Under Temperature Cycling

Miura, Hideo; Kitano, Makoto; Nishimura, A.; Kawai, Sueo

doi:10.1115/1.2909307

Cited by 34 publications

(9 citation statements)

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“…In another example, the temperature distribution in plastic packages was measured during the vaporphase and infrared reflow processes, as well as during a dip-coating process [32]. The thermal stress during temperature cycles has been measured using piezoresistive microsensors [26]. Viscoelasticity of the molding compound was identified as the reason of cyclic stress increase in the package.…”

Section: Packaging Characterization By Microsensorsmentioning

confidence: 99%

“…Microsensors permit nonintrusive in situ measurements [25][26][27][28][29][30][31][32][33][34][35][36][37]. Test chips with integrated microsensors for plastic package analysis were reported in considerable detail [11,25].…”

Section: Packaging Characterization By Microsensorsmentioning

confidence: 99%

“…Test chips with integrated microsensors for plastic package analysis were reported in considerable detail [11,25]. Such microsensors measure thermal stress [26,27], corrosion [28][29][30][31], and moisture [25,31]. Various test chips are commercially avail-able [38][39][40].…”

Section: Packaging Characterization By Microsensorsmentioning

confidence: 99%

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Microelectronic Bonding Processes Monitored by Integrated Sensors

Mayer¹,

Schwizer

2002

Sensors Update

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Real-time monitoring methods are beneficial for the control, optimization, and failure analysis of microelectronic packaging processes. The focus of this chapter is on the real-time monitoring of two widely used processes, soft solder die bonding and thermosonic ball bonding. The methods presented here use uniquely developed microsensors integrated on custom-made test chips using commercial double-metal CMOS processes.For the soft solder die bonding process, nine aluminum-based resistive temperature detectors were integrated on various locations on a test chip. The temperature was monitored during the placement of the test chip on the leadframe. The experimental results describe the wetting and spreading effects of the molten solder under the drip. Together with numerical results obtained with a transient thermal finite element model, the beginning of wetting can be quantified. For the soft solder PbSn10, wetting occurred around 30 ms after touch down. This method hence can be used to determine wetting times under different process conditions. The wetting time determines an upper limit of the throughput of the process.For the thermosonic ball bonding process, temperature and force sensors were integrated on test chips. The sensors are aluminum resistors and piezoresistive p + -and n + -diffused resistors placed around bond pads. A bond quality parameter can be derived from the temperature signal variation during bonding. The piezoresistive sensors permit the measurement of forces in the x-, y-, and z-directions simultaneously. The ultrasonic tangential force signal reached a typical value of 0.12 N on a 50 lm diameter contact zone and revealed significant process characteristics. Four process phases are identified which are necessary for a successful ball bond formation. These phases are assigned to initial stiction, sliding, bond growth, and deformation effects.

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Section: Packaging Characterization By Microsensorsmentioning

confidence: 99%

Section: Packaging Characterization By Microsensorsmentioning

confidence: 99%

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Microelectronic Bonding Processes Monitored by Integrated Sensors

Mayer¹,

Schwizer

2002

Sensors Update

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“…11, November 2005, pp. 866-873 shown to be related to mechanical stress [8][9][10][11][12][13][14][15]. However, when chips which have been thinned to several tens of micrometers are stacked into a three-dimensional arrangement, the influence of Au or Cu bump bonding at high temperature and pressure on the MOSFET characteristics has not been studied sufficiently.…”

Section: Introductionmentioning

confidence: 99%

Mobility change of MOSFETs in a chip-stacked multichip package

Ikeda¹,

Honda²,

Ogi³

et al. 2006

Electron. Comm. Jpn. Pt. II

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We studied the mobility change of MOSFETs in a chip‐stacked multichip package. A 6‐inch wafer that had the back ground to 50 µm thickness was diced into chips and a chip was cemented to a glass epoxy substrate with a nonconductive paste (NCP), and in addition, a second chip was bonded on the first chip in a flip chip arrangement. The interchip connection was made by thermocompression bonding of Au/Ni bumps formed on the upper and lower chips. The MOSFETs on the first chip had not shown changes in mobility before stacking the second chip, but after stacking the chip, the mobility of the pMOSFETs increased and the mobility of the nMOSFETs decreased. Before chip stacking, the first chip had been slightly convex, but after stacking it was deformed to a greatly concave shape. It is considered that the glass epoxy substrate or the NCP had undergone a plastic deformation during the thermocompression bonding of the chip and that the strain from this deformation remained after the thermocompression bonding process. As a consequence, bending compressive stress occurred in the first chip in the [1¯10] direction, and it is considered that the mobility of the MOSFET changed due to the piezoresistive effect. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(7): 1– 8, 2006; Published online in Wiley InterScience (http://www.interscience.wiley.com). DOI 10.1002/ecjb.20246

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“…The estimated results of the local thermal deformation and the residual thermal stress were validated by using a laser microscope and small piezoresistive stress sensors. [8]- [12] We have successfully developed a piezoresistive stress sensor chip with 2-µm long gauges that consisted of singlecrystalline silicon. The local distribution of the residual thermal stress on the active layers of each chip in two chipstacked structures assembled by flip-chip technology was measured by using this sensor chip.…”

Section: Introductionmentioning

confidence: 99%

Local electronic function shift in LSI chips stacked three-dimensionally by area-arrayed bump structures caused by local deformation of the laminated chips

Miura

Ueta

Sato

et al. 2008

2008 58th Electronic Components and Technology Conference

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The clear periodic thermal deformation and thus, the periodic thermal residual stress distribution appears in each chip in three-dimensionally stacked chip structures due to the periodic alignment of metallic small bumps when the thickness of a chip is decreased to less than 200 µm. The estimated local deformation was validated by using a scanning blue laser microscope. It reached about 180 nm when the thickness of the stacked chip was 100 µm. The local distribution of the residual thermal stress was also measured by using stress-sensing test chips which consisted of about 1400 2-µm-long strain gauges. It was found that the residual stress varied from -200 MPa to +100 MPa depending on the position of the chip in the stacked structure and the layout of the small bumps. Finally electronic function shift of transistors formed near the strain gauges were measured between two bumps. For example, the amplitude of a periodic distribution of the function change of 90-nm-gate NMOS transistors between two bumps reached about 8%. Therefore, it is very important to minimize the local thermal deformation and residual stress of three-dimensionally stacked chips to assure the reliable electronic performance of products.

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Thermal Stress Measurement in Silicon Chips Encapsulated in IC Plastic Packages Under Temperature Cycling

Cited by 34 publications

References 0 publications

Microelectronic Bonding Processes Monitored by Integrated Sensors

Microelectronic Bonding Processes Monitored by Integrated Sensors

Mobility change of MOSFETs in a chip-stacked multichip package

Local electronic function shift in LSI chips stacked three-dimensionally by area-arrayed bump structures caused by local deformation of the laminated chips

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