Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)

Chien, Heng-Chieh; Lau, John H.; Chao, Yu-Lin; Tain, Ra-Min; Dai, Ming-Ji; Wu, S. M.; Lo, Wei‐Chung; Kao, Ming-Jer

doi:10.4071/isom-2011-ta1-paper4

Cited by 9 publications

(6 citation statements)

References 14 publications

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“…The largest error of the empirical equations is less than 15%. Most simulation data agree with the equivalent equations to an error of less than 10% [12,16].…”

Section: Fig6 Schematic Diagram Of a Tsv Cellmentioning

confidence: 50%

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Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

Chien

Lau

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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In this investigation, the thermal and mechanical design and analysis of a TSV (through-silicon via) interposer which supports 2 active chips on its top-side and 1 active chip on its bottom-side (a real 3D IC integration with an interposer) are studied. Emphasis is placed on the thermal design and analysis of the chips' average temperatures and the applied cooling capability on the heat spreader/sink. To simplify the simulations, an equivalent model, that can preciously determine the thermal performances of TSVs and solder bumps/balls, is introduced instead of a complicate detail 3D model. Another emphasis is placed on the determination of the creep strain energy density per cycle of the solder bumps/balls between the chips and the TSV interposer, the TSV interposer and the organic package substrate, and the package substrate and the PCB (printed circuit board) under environmental thermal cycling condition.

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“…The largest error of the empirical equations is less than 15%. Most simulation data agree with the equivalent equations to an error of less than 10% [12,16].…”

Section: Fig6 Schematic Diagram Of a Tsv Cellmentioning

confidence: 50%

“…To convert the detailed model to the equivalent model, we use a conversion rule that is described in previous literatures [12,16]. In the conversion, the arrays of TSV, solder bump, Fig.…”

Section: (2) Thermal Characteristic Of the 3d Ic Integration Modulementioning

confidence: 99%

Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

Chien

Lau

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…In addition to the parameters used in Lau and Yue, [9] Table 1 has also included the parameter of SiO2 thickness, which results in a smaller planar equivalent thermal conductivity and a larger vertical equivalent thermal conductivity of TSV cell than the isotropic thermal conductivity of silicon. The studies of Chien et al [1,2] derived the empirical correlations of equivalent TSV thermal conductivities in planar and vertical directions. For the selective chip area having a cluster of TSVs, the TSV cell can be tiled together and then employ the empirical correlations of planar and vertical equivalent thermal conductivities for this TSV area.…”

Section: Introductionmentioning

confidence: 99%

“…In addition to the parameters used in Lau and Yue, [9] Table 1 has also included the parameter of SiO2 thickness, which results in a smaller planar equivalent thermal conductivity and a larger vertical equivalent thermal conductivity of TSV cell than the isotropic thermal conductivity of silicon. The studies of Chien et al [1,2] derived the empirical correlations of equivalent TSV thermal conductivities in planar and vertical directions. 10, 20, 30, 50, 100, 150 10, 20, 50, 100, 150, 200 10, 20, 50, 100, 150, 250 10, 20, 50, 100, 150, 250 10, 20, 50, 100, 150, 250 P(μm) 25, 35, 40, 50, 70, 100, 130 35, 45, 55, 65, 80, 120, 150 45, 55, 65, 75, 100, 150, 200 55, 65, 75, 85, 100, 150, 200 65, 75, 85, 100, 150, 200 TSVs.…”

mentioning

confidence: 99%

“…Thus, the evaluated values of equivalent thermal conductivities in planar and vertical directions are both larger than the isotropic thermal conductivity of the silicon. A 3D cell-based TSV structure is developed to investigate the anisotropic equivalent thermal conductivity properties by Chien et al [1,2] The TSV cell as shown in Fig. 1 includes a single cylindrical copper filling and is surrounded with a dielectric layer of SiO2.…”

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Thermal Performance of 3D IC Package with Embedded TSVs

Tain

Dai

Chao

et al. 2012

Transactions of The Japan Institute of Electronics Packaging

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more than two chips and these IC chips can be stacked up vertically and communicate with each other through vias.However, thermal challenge of the 3D IC chip stack becomes a limitation for using the TSVs because the heat spreading in the stack is less effective than non-stacked chips. [4,5] Therefore, thermal performance is the major concern for vertical IC chip stack. TSV is a metal-filled component embedded in a silicon chip, where a dielectric layer (e.g. silicon dioxide, SiO 2 ) is deposited between the bulk silicon and the metal filling. The thermal conductivity of SiO2 layer is orders of magnitude less than that of metal filling, e.g. the copper. Thus, the thermal property for a TSV or a TSV group is much better in vertical direction than in the planar direction.Thermal solutions for stacked IC structure have been proposed and investigated from literature. [6,7] Experiment results and simulation analyses have also been reported, especially for the TSV thermal behavior. [4,5,8,9] Oprins et al. [8] has designed and fabricated a test chip as well as conducted the measurements of thermal performance for the test vehicle, which one thinned chip with TSV is bonded on top of a thick chip without TSV using Rm.168, Bldg.14, No.195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu 31040, Taiwan (Received July 23, 2012; accepted November 5, 2012) Abstract A two-chip stacking 3D IC with 0.18 μm technology has been mounted in a QFP package for conducting measurement of thermal resistance from junction to the package case surface (bottom). The thermal resistances for the layers of chips, micro bumps, underfill resin between chips, and ceramic substrate are also being analyzed with the thermal RC model theory and the cumulative structure function. The top chip is embedded with through-silicon vias (TSVs) and is thinned down to 60 μm thick. The bottom chip has no TSV and the thickness is the same as a normal IC chip. Both chips have the same layout and include two types of heaters. The first heater is designed to emulate a hot spot and is located at the chip center. The second heater, with heat flux level (uniform heating) close to 1/20 of the first heater, is designed to heat up the surrounding area of the first heater. A simulation model of the QFP package is developed and a set of equivalent thermal conductivity correlations in planar (xy) and vertical (z) directions of TSVs are used in order to simplify the simulation model and shorten the computational time. Comparisons between simulation models show that the result is accurate for uniform heating condition and satisfactory for hot spot heating condition.Keywords: 3D IC, Through Silicon Via, Chip Stacking, Thermal Conductivity, QFP Package 76Transactions of The Japan Institute of Electronics Packaging Vol. 5, No. 1, 2012 analysis in design phases. Lau and Yue[9] studied the equivalent thermal conductivities in planar and vertical directions for 3D IC structure with TSVs embedded in stacked chips in simulations. The simulation results of equivalent thermal conducti...

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2.5D IC Integration

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2021

Semiconductor Advanced Packaging

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Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)

Cited by 9 publications

References 14 publications

Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

Thermal Performance of 3D IC Package with Embedded TSVs

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