Thermal Modeling of a Chiplet-Based Packaging With a 2.5-D Through-Silicon Via Interposer

Zhou, Minghao; Li, Li; Hou, Fengze; He, Guanglong; Fan, Jiaqi

doi:10.1109/tcpmt.2022.3174608

Cited by 14 publications

(4 citation statements)

References 29 publications

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“…Due to the advantages of miniaturization, high performance, and low cost, Chiplet-based systems have been applied in computing systems and processing-in-memory systems [ 4 , 5 , 6 ]. Through silicon via (TSV) is a key technology to achieve vertical interconnection between different dies in Chiplet-based systems [ 7 , 8 , 9 , 10 , 11 ]. In order to satisfy the requirements of various applications, cylindrical, tapered, and coaxial TSVs (CTSVs) have been proposed [ 12 , 13 , 14 ].…”

Section: Introductionmentioning

confidence: 99%

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

Wang

Chen

et al. 2023

Micromachines

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In this research, an efficient thermal-stress coupling design method for a Chiplet-based system with a coaxial through silicon via (CTSV) array is developed by combining the support vector machine (SVM) model and particle swarm optimization algorithm with linear decreasing inertia weight (PSO-LDIW). The complex and irregular relationship between the structural parameters and critical indexes is analyzed by finite element simulation. According to the simulation data, the SVM model is adopted to characterize the relationship between structural parameters and critical indexes of the CTSV array. Based on the desired critical indexes of the CTSV array, the multi-objective evaluation function is established. Afterwards, the structural parameters of the CTSV array are optimized through the PSO-LDIW algorithm. Finally, the effectiveness of the developed method is verified by the finite element simulation. The simulated peak temperature, peak stress of the Chiplet-based system, and peak stress of the copper column (306.16 K, 28.48 MPa, and 25.76 MPa) well agree with the desired targets (310 K, 30 MPa, and 25 MPa). Therefore, the developed thermal-stress coupling design method can effectively design CTSV arrays for manufacturing high-performance interconnect structures applied in Chiplet-based systems.

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Section: Introductionmentioning

confidence: 99%

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

Wang

Chen

et al. 2023

Micromachines

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“…These challenges have further driven the industry to shift from SoC to heterogeneous system integration and scaling with advanced packaging, such as system-in-package (SiP) and system-on-package (SoP). These heterogeneous integration (HI) packaging solutions enable the integration of advanced packages [1,2], chips/chiplets [3], passive devices, and functional electronic components from various manufacturers with diversified manufacturing processes into a single package or module. They offer compelling efficiency, durability, flexibility, increased function density, and a more reasonable development and design cost, as well as good electrical performance, yield improvement, intellectual property reusability, and even miniaturization.…”

Section: Introductionmentioning

confidence: 99%

“…Presently, SiP and SoP have been effectively fulfilled using various advanced packaging technologies in a two-dimensional (2D) planar, two-and-a-half dimensional (2.5D) [3,4], or three-dimensional (3D) IC packaging configuration [5], such as package-in-package (PiP) [4], package-on-package (PoP) [6,7] using flip chip chip-scale packaging (FCCSP) [8,9], and flip chip ball grid array (FCBGA) packaging [10], and 3D IC integration with through silicon vias (TSVs) silicon or glass interposers [3,4,11,12]. When fulfilling these HI packaging technologies, high-density interconnect (HDI) IC substrates and interposers play a crucial role in providing electrical connection between the IC chip and the printed circuit board (PCB) and mechanical support and heat dissipation for IC chips.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, they play a dominant and essential role in the thermomechanical behavior of the electronic assemblies, driven by the mismatch between temperature and the coefficient of thermal expansion (CTE) among the constituent materials. Presently, many studies have been carried out to assess the thermal performance, reliability, and warpage of various laminate substrate-based IC packages and assemblies (see, e.g., [1][2][3][4]7,9,10,13]). Normally, this can be achieved using direct detailed finite element analysis (DD-FEA).…”

Section: Introductionmentioning

confidence: 99%

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Effective Macroscopic Thermomechanical Characterization of Multilayer Circuit Laminates for Advanced Electronic Packaging

Cheng,

Jhu

2023

Materials

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Laminate substrates in advanced IC packages serve as not only the principal heat dissipation pathway but also the critical component governing the thermomechanical performance of advanced packaging technologies. A solid and profound grasp of their thermomechanical properties is of crucial importance to better understand IC packages’ thermomechanical behavior. This study attempts to introduce a subregion homogenization modeling framework for effectively and efficiently modeling and characterizing the equivalent thermomechanical behavior of large-scale and high-density laminate substrates comprising the non-uniform distribution and non-unidirectional orientation of tiny metal traces. This framework incorporates subregion modeling, trace mapping and modeling, and finite element analysis (FEA)-based effective modeling. In addition, the laminates are macroscopically described as elastic orthotropic or elastic anisotropic material. This framework is first validated with simple uniaxial tensile and thermomechanical test simulations, and the calculation results associated with these two effective material models are compared with each other, as well as with those of two existing mixture models, and direct the detailed FEA. This framework is further tested on the prediction of the process-induced warpage of a flip chip chip-scale package, and the results are compared against the measurement data and the results of the whole-domain modeling-based effective approach and two existing mixture models.

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System technology co-optimization for advanced integration

Pal,

Mallik,

Gupta

2024

Nat Rev Electr Eng

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Thermal Modeling of a Chiplet-Based Packaging With a 2.5-D Through-Silicon Via Interposer

Cited by 14 publications

References 29 publications

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

Efficient Thermal-Stress Coupling Design of Chiplet-Based System with Coaxial TSV Array

Effective Macroscopic Thermomechanical Characterization of Multilayer Circuit Laminates for Advanced Electronic Packaging

System technology co-optimization for advanced integration

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