Thermal modeling and management in ultrathin chip stack technology

Abstract

Abstract-This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (

Impact of the number of chips on the reliability of the solder balls for wire-bonded stacked-chip ball grid array packages

“…The stacked chip package structure is designed to include more than one chip, so the thermal management of such packages has become very important, and some efforts have been made to yield solutions, by both experimental and simulation analyses [9][10][11][12][13][14][15][16]. The reliability of stacked chip packages is another subject to be addressed.…”

Dynamic compact thermal models with multiple power sources: application to an ultrathin chip stacking technology

“…In the problem at hand, the concurrent presence of several very close power sources and the use of low thermal conductivity materials was considered as the rationally for starting a full set of simulations at the physical level. Main conclusions of this study were presented elsewhere [15].…”

Simulation and FPGA Implementation of a Ring Oscillator Sensor for Complex System Design

“…The future of detectors based on the ring oscillator method is to help designers of more complex integrated circuits to optimize the management of thermal dynamics on the chip [7], [8] and [9]. In this paper in particular, the sensor used allows the detection of thermal peaks.…”