Proceedings IEEE COMPCON 97. Digest of Papers
DOI: 10.1109/cmpcon.1997.584744
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Thermal management system for high performance PowerPC/sup TM/ microprocessors

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Cited by 87 publications
(57 citation statements)
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“…For example, one could use thermal sensory data to have the processor switch between the two techniques, depending on current thermal or performance concerns. Related but simpler approaches are already found in commercial processors; for example, the IBM/Motorola PPC750 is equipped with an on-chip thermal assist unit and temperature sensor which responds to thermal emergencies by controlling the instruction fetch rate through I-cache throttling [21].…”
Section: Operation Packingmentioning
confidence: 99%
“…For example, one could use thermal sensory data to have the processor switch between the two techniques, depending on current thermal or performance concerns. Related but simpler approaches are already found in commercial processors; for example, the IBM/Motorola PPC750 is equipped with an on-chip thermal assist unit and temperature sensor which responds to thermal emergencies by controlling the instruction fetch rate through I-cache throttling [21].…”
Section: Operation Packingmentioning
confidence: 99%
“…DPM aims to shut off system parts (inside or outside the CPU) that are not in use at any given time. Execution bandwidth throttling has also recently been proposed, in which the number of instructions fetched per cycle is reduced [17] or the frequency of fetch operations is varied [1,21]. Structure resizing for power reduction has also been considered.…”
Section: Related Workmentioning
confidence: 99%
“…The trigger temperature is a thermal limit over which a dynamic predictive/reactive thermal management schemes will be initiated whereas the emergency temperature is a thermal limit over which the chip may be damaged and hence must be avoided at all cost. Those DTM schemes include architectural adaptations such as fetch-toggling [1] (instruction fetching is stalled for next N cycles), instruction cache throttling [2] (throttle the instruction forwarding from the instruction cache to the instruction buffer), activity migration [3] (dispatching computations to different locations on the die) and dynamic voltage and frequency scaling [4] (DVFS). Those DTM schemes are application-independent schemes.…”
Section: Introductionmentioning
confidence: 99%