2018
DOI: 10.3788/fgxb20183907.0983
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Thermal Impact of High Power Semiconductor Laser with Voids in Solder Layer

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“…According to the research, the junction temperature of the device will have a significant temperature rise when the cavity is located in the active light‐emitting region, and other positions have less influence on the temperature rise of the device, and for a single large cavity and multiple discrete cavities of the same area In general, large voids have a greater impact on the temperature rise of the device, and discrete small voids have a small effect on the temperature rise of the device 19 …”
Section: Void Estimation Methodsmentioning
confidence: 96%
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“…According to the research, the junction temperature of the device will have a significant temperature rise when the cavity is located in the active light‐emitting region, and other positions have less influence on the temperature rise of the device, and for a single large cavity and multiple discrete cavities of the same area In general, large voids have a greater impact on the temperature rise of the device, and discrete small voids have a small effect on the temperature rise of the device 19 …”
Section: Void Estimation Methodsmentioning
confidence: 96%
“…According to the research, the junction temperature of the device will have a significant temperature rise when the cavity is located in the active lightemitting region, and other positions have less influence on the temperature rise of the device, and for a single large cavity and multiple discrete cavities of the same area In general, large voids have a greater impact on the temperature rise of the device, and discrete small voids have a small effect on the temperature rise of the device. 19 Therefore, to facilitate the study of the effect of voids on the temperature rise of the device, in the analysis, the positions of the proposed solder voids are located in the active light-emitting area of the device and the thickness of the solder is the same. The size of 0 μm < d ≤ 500 μm, the relationship between the cavity diameter d and the device junction temperature T is shown in Figure 4A.…”
Section: Void Estimation Methodsmentioning
confidence: 99%