2016 17th International Conference on Electronic Packaging Technology (ICEPT) 2016
DOI: 10.1109/icept.2016.7583176
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Thermal evaluation of partially molded 2.5D package with pin fin heat sink cooling

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Cited by 3 publications
(3 citation statements)
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“…First, high- performance chips are laterally placed close to each other while their temperature-sensitivity and mechanical-reliability metrics are different. This is a common scenario in 2.5D package platforms [28,46,79,[82][83][84][85][86][87][88][89][90][91][92][93]. Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips.…”
Section: Thermal Management Challenges In Heterogeneousmentioning
confidence: 99%
See 1 more Smart Citation
“…First, high- performance chips are laterally placed close to each other while their temperature-sensitivity and mechanical-reliability metrics are different. This is a common scenario in 2.5D package platforms [28,46,79,[82][83][84][85][86][87][88][89][90][91][92][93]. Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips.…”
Section: Thermal Management Challenges In Heterogeneousmentioning
confidence: 99%
“…This requires effective cooling very close to the heat source. However, some of the 2.5D packages have various layers, such as TIM and heat slug layers, between the heat source and the heat sink for reliability concerns at the board level [83,85,89,92]. When the heat sink has a rough contact surface and the 2.5D package has a large thermally induced or assembly warpage, the possibility of the active device cracking and failure increases after the heat sink is attached.…”
Section: Thermal Management Challenges Due To Multichipmentioning
confidence: 99%
“…As shown in Figure 1 a, a Teflon-based thermal PCB was designed for packaging the chip to ensure efficient heat dissipation by incorporating optimized thermal vias in the design [ 10 ]. Research for work for the thermal enhancements of 2.5D is done by bridging the thermal path from the die to the top heat sink directly without molding material [ 11 ] as depicted in Figure 1 b. The other work used a new photo-imageable solder resist (PSR) that has high thermal conductivity to reduce the junction temperature of the chip [ 12 ].…”
Section: Introductionmentioning
confidence: 99%