Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications

Abstract

In this study, we used simulation technique to analyze the thermal behaviors and investigate the thermal issues of a designed system in package (SiP) for network system application that based on a three dimensional integrated circuit (3D IC) structure. The 3D IC SiP has an interposer which with regularly embedded through-silicon vias (TSVs); there are one CPU chip and two DRAM chips planted on the top side and bottom side of the interposer, respectively. The interposer with chips is bonded on a BT substrate; the BT substrate is bonded on a PCB; and a metallic heat spreader is placed on and glued to the CPU chip's back-side. Because a 3D IC SiP with TSVs is so complicate for modeling and very difficult for meshing, this study attempted to use the equivalent models of embedded TSV, bump/solder bond and metallic trace to simplify a detail 3D IC model. We introduced a slice model, that four stacked chips on an interposer and each chip has two heaters and TSVs, to verify the accuracy and feasibility of the equivalent model by comparing to the detail model, the results of both models show that they are in a good agreement. By using the equivalent model to simulate the studied 3D IC integrated SiP; we found the CPU temperature would be dominated by the cooling capability of a thermal module that attached on the heat spreader. As for the DRAM chips that underneath the interposer, it is inevitable to have a quite high temperature due to the temperature superposition effect and an obstructed heat flow path. In fact, the severely high temperature of the chips under an interposer should be the main thermal issue for such a 3D IC SiP because there is no easy thermal solution for these chips.

Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips

“…The largest error of the empirical equations is less than 15%. Most simulation data agree with the equivalent equations to an error of less than 10% [12,16].…”

“…To convert the detailed model to the equivalent model, we use a conversion rule that is described in previous literatures [12,16]. In the conversion, the arrays of TSV, solder bump, Fig.…”

Thermal-mechanical responses of 3D IC integration with a passive TSV interposer

“…It can be seen that an interposer with TSVs is supporting a high-performance chip on its top side and another chip on its bottom-side. These chips are arranged into a face-to-face situation so as to achieve better electrical performance [21][22][23][24].…”

An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias

“…Feng et al [23] proposed an equivalent thermal model for 2.5D packages, and the calculation time was reduced from 15 min to 23 s. Lau et al [24] also investigated the thermal performance of three-layer-stacked chips using the computational fluid dynamics analysis method, and the empirical formula of effective thermal conductivity was proposed. Heng [25] proposed an equivalent model considering TSV, bump, and metallic trace, which could effectively improve the calculation efficiency of 3D system in package (SiP). Chen et al [26] established an equivalent thermal resistance model for TSV, and the thermal performance of a 3D stacked-die package with TSV was quickly estimated by the proposed model.…”