Thermal-Driven Analog Placement Considering Device Matching

Abstract

With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices. There is not much previous work that considers the desired placement configuration between power and thermally-sensitive devices for a better thermal profile to reduce the thermally-induced mismatches. In this paper, we first introduce the properties of a desired thermal profile for better thermal matching of the matched devices. We then propose a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and the common-centroid constraints. Experimental results based on real analog circuits show that our approach can achieve the best analog circuit performance/accuracy with the least impact due to the thermal gradient, among existing works.

A Novel Optimal 2-D Layout for Cache Memory at 45nm CMOS Technology

“…In [4], Center based corner block list (c-cbl) has given by Qiang Ma, which is a natural extension of corner block list (cbl) to represent a common centroid placement of a set of device pair to maintain the performance and stability of a circuit and it is desirable to restrict all the devices of a common centroid group to form a cluster in the final placement, without interleaving with other blocks not in the same group. Experimental results show that given approach is fast and have high scalability and handle effectively, and placements satisfying the constraints can be generated efficiently with an average dead space of 8.29%.…”

State of the Art on Analog Layout Automation

“…In a different direction from the other emerging works, Lin et al [18] proposed a thermal-driven analog placement solution, to simultaneously optimize the placements of ''power'' and ''non-power'' (devices which consume much less power than those classified as ''power'') devices, in an attempt to annihilate thermally-induced mismatches. It is known that the thermal impact from ''power'' devices can affect the electrical characteristics of the other thermally-sensitive modules, degrading analog and mixed-signal ICs performance.…”

“…Ranjan [33] ALDAC [30] KOAN/ANAGRAM [27] ALADIN [23] LAYLA [28] Castro-Lopez [31] Zhang [25] Malavasi [29] Koda [16] Lin [18] ALG [24] Habal [35] Jingnan [20] Vancorenland [32] ALSYN [19] Legend:…”

A Method of Analog IC Placement with Common Centroid Constraints

“…In order to obtain placement which satisfies common centroid constraint, some methods are proposed [4,5,6,7,8]. Strasser et al proposed a method using B * -tree [4], but this method is deterministic.…”

“…Strasser et al proposed a method using B * -tree [4], but this method is deterministic. P. H. Lin et al proposed a thermal-driven common centroid placement algorithm [5], and C. W. Lin et al proposed a method to obtain placement considering random mismatches [6]. Both methods [5,6] can handle unit-capacitors only.…”