Thermal Aware Placement in 3D ICs

Abstract

Dominance of on-chip power densities has become a critical design constraint in high-performance VLSI design. This is primarily due to increased technology scaling, number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entail the stacking of multiple active (device) layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the thermal placement of standard cells and gate arrays (modules) taking total wire-length as well as TSVs (through silicon via) into consideration. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of the active layers are not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer, (iv) the estimated total interconnect lengths connecting the modules of the different layers are also improved, and (v) the total number of interlayer vias is quite reasonable. Experimental results on randomly generated and standard benchmark instances are encouraging.

Thermal placement on PCB of components including 3D ICs

“…Thermal-aware 3D network-on-chip (NoC) designs have been proposed [10,11]. Related to the thermal placement of 3D ICs, thermal through-silicon-via (TSV) optimization [12,13,14,15,16] and thermal floor plans [17,18,19,20,21,22,23,24,25,26] have been presented. Placement optimization of chips in SoP designs has been presented [27].…”

An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI

“…The die boundary wall has an adiabatic influence on the internally generated heat and the temperature of a functional block is characterized by its relative position from the die boundary wall. These thermal considerations have been ignored by the works done till now on MSP [5], [11] - [14] for the thermal aware placement. Moreover, the experimental works done in [5], [11] - [14] have not quantified the thermal improvements in terms of temperature.…”

“…These thermal considerations have been ignored by the works done till now on MSP [5], [11] - [14] for the thermal aware placement. Moreover, the experimental works done in [5], [11] - [14] have not quantified the thermal improvements in terms of temperature. The experimental works done in [5], [11] - [14] considers only square matrix formation for cell placement thereby incurring more dummy cells to make up a square number of total cells.…”

“…Moreover, the experimental works done in [5], [11] - [14] have not quantified the thermal improvements in terms of temperature. The experimental works done in [5], [11] - [14] considers only square matrix formation for cell placement thereby incurring more dummy cells to make up a square number of total cells. Dummy cells are proxy blocks having zero power dissipation and the inclusion of more dummy cells increase the chip area.…”

Thermal management of 3D integrated circuits with microchannel-based liquid cooling

“…A lot of research effort has then been spent on auxiliary techniques to supplement the air cooling. Some of the representative techniques are thermal-aware floorplan and placement, task scheduling and thermal TSVs [169,170,175,176,216,217,262]. Unfortunately, for 3DICs with high power density or more than two circuit layers, the long heat transfer path dominates and the temperature of circuits far from the heatsink can easily rise to an unacceptable level.…”