Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures

Abstract

The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.

Impact of phonon scattering in Si/GaAs/InGaAs nanowires and FinFets: a NEGF perspective

“…Another important issue is power dissipation in ultra-highscale 3D integration [18][19][20]. Miniaturization compresses a huge number of devices into a small region and, when combined with the heat partially trapped inside the channel of a 3D MOSFET, makes heat release a difficult enterprise.…”