Theory and Applications of Incremental<tex>$Delta Sigma $</tex>Converters

Abstract

Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (16) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the 16 converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results. Index Terms-Charge balancing delta-sigma (16) modulator, decimating filter, dither, incremental (integrating) analog-digital (A/D) converter, no-latency 16 converter, one-shot 16 converter, staggered zeros, switched-capacitor circuit.

A comparative design study of continuous‐time incremental sigma‐delta ADC architectures

“…2-4. For IΣ∆ ADCs with a feed-forward topology, the conversion residue can be obtained directly at the output of the last integrator [1]. This property provides the possibility to reduce the quantization error by digitizing the residue and combining it with the decimated modulator output.…”

“…To estimate the maximum achievable theoretical resolution of different ADC architectures, timedomain analysis [1,19] was performed to derive the output of the last integrator after M cycles as well as the quantization error of each conversion. The main differences of CT IΣ∆ ADCs with respect to their DT counterparts are the derivation of the loop filter coefficients as well as the design of the digital filter [17].…”

“…Mod2 ER 2Step s1 2Step s2 R dac 500kΩ 500kΩ 500kΩ 780kΩ R 1 500kΩ 500kΩ 500kΩ 780kΩ R 2 390kΩ 780kΩ 780kΩ 1000kΩ C 1 1.56pF 15.6pF 15.6pF 10pF C 2 1.25pF 5pF 5pF 3.9pF Figure 12. Schematics of (a) the 2 nd -order CT IΣ∆ modulator and (b) the SH in the CT-IΣ∆ 2Step .…”

“…Incremental sigma-delta (Σ∆) analog-to-digital converters (ADCs) are commonly used in instrumentation and biosensor applications [1,2], which typically feature signal bandwidth from kilohertz to megahertz and medium-to-high resolution. Unlike conventional Σ∆ ADCs, the analog loop filter and digital filter in IΣ∆ ADCs are reset after oversampling each input sample.…”

Design of interpolative sigma delta modulators via a semi-infinite programming approach

“…The popularity of SDMs is mainly due to their simple, inexpensive and robust circuit implementations, as well as achieving very high SNR because of their ability to perform noise shaping [4]. SDMs are typically designed using Butterworth filter design rules [5], and optimal designs have been performed via HSpice [6], Matlab [7] and Fortran [8]. Although these designs have considered many practical issues, the solutions obtained are not the global optimal one.…”