Theoretical Study of Some Physical Aspects of Electronic Transport in nMOSFETs at the 10-nm Gate-Length

Fischetti, Massimo V.; O’Regan, Terrance; Narayanan, Sudarshan; Sachs, C.; Jin, Shaohua; Kim, Jiseok; Zhang, Yan

doi:10.1109/ted.2007.902722

Cited by 112 publications

(67 citation statements)

References 58 publications

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“…No quantum transport effects are included in this model, and the case of fully ballistic transport has not been extensively considered. Fischetti et al 38 argued that fully ballistic transport is impossible to achieve -even for ultra-short devices-owing to long range Coulomb interactions between FIG. 8.…”

Section: Discussionmentioning

confidence: 99%

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

2015

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Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.

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Section: Discussionmentioning

confidence: 99%

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

2015

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“…This effect has been called "source exhaustion" [46,47]. Its effect on the transistor's IV characteristics is similar to that produced by the "source starvation" effect discussed by Fischetti [14,19], but it is simply consequence of electrostatics. Our simulations do not capture the source access and source starvation effects, but they do include the possibility of source exhaustion.…”

Section: Source Design Issuesmentioning

confidence: 86%

“…Fischetti and Laux have pointed out the importance of source design considerations such as access geometry and source starvation for III-V transistors [14,18,19]. The first issue refers to the fact that the source access geometry may restrict the flow of carriers into the channel.…”

Section: Source Design Issuesmentioning

confidence: 99%

“…Recent innovations on III-V transistors include sub-100 nm gate-length, high performance InGaAs buried channel [4,5] and surface channel MOSFETs [6], sub-80 nm E-mode InGaAs/InAs HEMTs [7][8][9][10], and InSb p-channel HEMTs [11] with outstanding logic performance at short channel lengths and low supply voltages. At the same time, theoretical work has predicted the performance of III-V transistors with respect to Si at near future technology nodes with the focus on device design, bandstructure effects, source engineering, etc [12][13][14][15][16][17][18][19][20][21].…”

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confidence: 99%

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Device Physics and Performance Potential of III-V Field-Effect Transistors

Liu

Pal²,

Lundstrom³

et al. 2010

Fundamentals of III-V Semiconductor MOSFETs

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The device physics and technology issues for III-V transistors are examined from a simulation perspective. To examine device physics, an InGaAs HEMT structure similar to those being explored experimentally is analyzed. The physics of this device is explored using detailed, quantum mechanical simulations based on the non-equilibrium Green's function formalism. In this chapter, we: (1) elucidate the essential physics of III-V HEMTs, (2) identify key technology challenges that need to be addressed, and (3) estimate the expected performance advantage for III-V transistors. IntroductionDriven by tremendous advances in lithography, the semiconductor industry has followed Moore's law by shrinking transistor dimensions continuously for the last 40 years. The big challenge going forward is that continued scaling of planar, silicon, CMOS transistors will be more and more difficult because of both fundamental limitations and practical considerations as the transistor dimensions approach ten nanometers. The issues at small gate lengths are many fold. First, transistor scaling increases the number of gates on a chip and the operating frequency. To prevent the chip from overheating, the power dissipation should be limited, which requires lowering the power supply voltage while maintaining the ability to deliver high oncurrents for each new generation of technology. Secondly, the drain bias decreases the energy barrier height between the source and channel in a transistor due to 2D electrostatics. Degraded short channel effects become more significant as the gate length gets shorter, and the increased off-state leakage has pushed the standby power to its practical limit. Thirdly, the accompanying scaled oxide thickness provides better gate control of the channel potential, but this inevitably increases S. Oktyabrsky, P. D. Ye (eds.), Fundamentals of III-V Semiconductor MOSFETs,

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“…Since most of the available models are one-dimensional, the currently most popular approach to calculate Zener current in a device is to choose a set of one-dimensional tunnel paths and to determine the tunneling probability along these paths within the WKB approximation [12,13]. However, as all one-dimensional models ignore the pronounced twodimensional shape of a realistic potential profile, the development of a more comprehensive calculation of Zener tunneling in semiconductors is in order.…”

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confidence: 99%

Generalized phonon-assisted Zener tunneling in indirect semiconductors with non-uniform electric fields: A rigorous approach

Vandenberghe

Sorée

Magnus

et al. 2011

Journal of Applied Physics

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A general framework to calculate the Zener current in an indirect semiconductor with an externally applied potential is provided. Assuming a parabolic valence and conduction band dispersion, the semiconductor is in equilibrium in the presence of the external field as long as the electronphonon interaction is absent. The linear response to the electron-phonon interaction results in a non-equilibrium system. The Zener tunneling current is calculated from the number of electrons making the transition from valence to conduction band per unit time. A convenient expression based on the single particle spectral functions is provided, enabling the evaluation of the Zener tunneling current under any three-dimensional potential profile. For a one dimensional potential profile an analytical expression is obtained for the current in a bulk semiconductor, a semiconductor under uniform field and a semiconductor under a non-uniform field using the WKB (WentzelKramersBrillouin) approximation. The obtained results agree with the Kane result in the low field limit.A numerical example for abrupt p − n diodes with different doping concentrations is given, from which it can be seen that the uniform field model is a better approximation than the WKB model but a direct numerical treatment is required for low bias conditions.

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Theoretical Study of Some Physical Aspects of Electronic Transport in nMOSFETs at the 10-nm Gate-Length

Cited by 112 publications

References 58 publications

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

Device Physics and Performance Potential of III-V Field-Effect Transistors

Generalized phonon-assisted Zener tunneling in indirect semiconductors with non-uniform electric fields: A rigorous approach

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