Device Physics and Performance Potential of III-V Field-Effect Transistors

Abstract

The device physics and technology issues for III-V transistors are examined from a simulation perspective. To examine device physics, an InGaAs HEMT structure similar to those being explored experimentally is analyzed. The physics of this device is explored using detailed, quantum mechanical simulations based on the non-equilibrium Green's function formalism. In this chapter, we: (1) elucidate the essential physics of III-V HEMTs, (2) identify key technology challenges that need to be addressed, and (3) estimate the expected performance advantage for III-V transistors. IntroductionDriven by tremendous advances in lithography, the semiconductor industry has followed Moore's law by shrinking transistor dimensions continuously for the last 40 years. The big challenge going forward is that continued scaling of planar, silicon, CMOS transistors will be more and more difficult because of both fundamental limitations and practical considerations as the transistor dimensions approach ten nanometers. The issues at small gate lengths are many fold. First, transistor scaling increases the number of gates on a chip and the operating frequency. To prevent the chip from overheating, the power dissipation should be limited, which requires lowering the power supply voltage while maintaining the ability to deliver high oncurrents for each new generation of technology. Secondly, the drain bias decreases the energy barrier height between the source and channel in a transistor due to 2D electrostatics. Degraded short channel effects become more significant as the gate length gets shorter, and the increased off-state leakage has pushed the standby power to its practical limit. Thirdly, the accompanying scaled oxide thickness provides better gate control of the channel potential, but this inevitably increases S. Oktyabrsky, P. D. Ye (eds.), Fundamentals of III-V Semiconductor MOSFETs,

Source/Drain Doping Effects and Performance Analysis of Ballistic III-V n-MOSFETs

“…This is the so-called "source exhaustion," where the lowdoped source cannot provide enough carriers at the strong ON-state [3], [6]. Also note that there is little orientation dependence visible between InAs <100> and <110> NWs in Fig.…”

“…One of them is the low solubility of dopants [2], which limits the source/drain (S/D) doping density (N SD ). This has been a concern mainly due to the parasitic resistance and the integrity of S/D electrostatics [3]. In extremely scaled transistors, however, N SD may also have more fundamental effects on the carrier transport within the device.…”

Nanoscale Semiconductor “X” on Substrate “Y” – Processes, Devices, and Applications

“…Recently, there has been a strong drive to integrate ultrathin layers of compound semiconductors on Si substrates for low power MOSFETs with the enabled integrated circuits (ICs) operating at voltages as low as V DD ∼ 0.5 V, which is ∼ 2x lower than that of the current state-of-the-art Si ICs. [47][48][49][50][51][52] However, there are signifi cant challenges in the fabrication process. Specifi cally, given the large lattice mismatch of Si and III-V semiconductors, heteroepitaxial growth techniques often require the deposition of a thick buffer layer for compensating the large lattice mismatch followed by the deposition of the active layer ( Figure 2 a).…”

III–V tri-gate quantum well MOSFET: Quantum ballistic simulation study for 10 nm technology and beyond

“…From the linear region of Id-Vd characteristics, we can extract ballistic carrier mobility in the channel. Carrier mobility for a non-planar device structure can be extracted from linear region of Id-Vd characteristics using the following relationship [17]:…”

“…The process is a bit more simplified and computationally efficient. With proper choice of device parameters, this approach can match experimental results with reasonable accuracy [17], [18]. Therefore, we have opted for a simplified fast uncoupled mode space approach with effective mass Hamiltonian.…”