2014
DOI: 10.3389/fphy.2014.00061
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Theoretical and experimental investigation of low-volgage and low-loss 25-Gbps Si photonic crystal slow light Mach–Zehnder modulators with interleaved p/n junction

Abstract: In this study, we investigated the performance of Si lattice-shifted photonic crystal waveguide (LSPCW) Mach-Zehnder modulators theoretically and experimentally. The LSPCW increases the phase shift in modulator to 2.3-2.5 times higher, which allows for size reduction and high performance. On-chip passive loss was reduced to less than 5 dB by optimizing each component. We obtained 25 Gbps clear open eye and 3 dB extinction ratio at a drive voltage of 1.5-1.75 V for 200 μm phase shifter with linear p/n junction … Show more

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Cited by 19 publications
(14 citation statements)
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“…Moreover, an interleaved p-n junction was employed, which increases the overlap of a depletion region with the slow-light mode and thus increases ∆n eq . This succeeded in the 25 Gbps modulation in a device with L = 200 µm with a drive voltage of V pp = 1.75 V (on the panel of pulse pattern generator, PPG) [15]. In this study, we observed an ER of 3 dB, although the excess modulation loss (ML), which usually helps to increase the ER, was moderately suppressed to 0.8 dB.…”
Section: Introductionmentioning
confidence: 51%
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“…Moreover, an interleaved p-n junction was employed, which increases the overlap of a depletion region with the slow-light mode and thus increases ∆n eq . This succeeded in the 25 Gbps modulation in a device with L = 200 µm with a drive voltage of V pp = 1.75 V (on the panel of pulse pattern generator, PPG) [15]. In this study, we observed an ER of 3 dB, although the excess modulation loss (ML), which usually helps to increase the ER, was moderately suppressed to 0.8 dB.…”
Section: Introductionmentioning
confidence: 51%
“…In general, f3dB is constrained by the RC time constant. We have reported the calculation of the resistance R and capacitance C at the p-n junction using the commercial simulator Lumerical DEVICE in Reference [15]. Modeling the Si layer sandwiched by the SiO2 BOX layer and top SiO2 cladding (both insulators), they were calculated to be 96 Ω (146 Ω including 50 Ω internal resistance in the PPG connected in series with the R) and ~60 fF at Vb = −2.2 × 2 V, respectively, for the current design.…”
Section: Frequency Responsementioning
confidence: 99%
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