The Verilog Procedural Interface for the Verilog Hardware Description Language

Dawson, Charles; Pattanam, Sathyam; Roberts, D.

doi:10.1109/ivc.1996.496013

Cited by 17 publications

(8 citation statements)

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“…If there are more than three, only the first three should be given followed by et al Please provide the missing author names in Refs. [1,2,4,5,6,7,8,9,10,11,13,14,16,17,18,19,20,21].…”

Section: Q4mentioning

confidence: 99%

Study of the monte–carlo fault injection simulator to measure a fault derating

Lee

2019

IET Computers & Digital Techniques

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The SER of the selected circuits can be determined via radiation tests. However, the time and costs required to perform radiation tests are prohibitive. Here, the authors introduce an accelerated Monte-Carlo fault injection (MCFI) method that can solve the slow execution time problem of the previous MCFI method using a modified simulator that uses the Verilog Procedural Interface (VPI). To demonstrate the performance of authors' accelerated MCFI tool, the authors perform a faultinjection campaign using the ISCAS85 and ITC99 benchmark circuits. Compared with the results from previous studies, the authors obtain an accurate logical derating rate value with a 3% variance, and the authors accelerate the execution time by 20 times or more.

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“…If there are more than three, only the first three should be given followed by et al Please provide the missing author names in Refs. [1,2,4,5,6,7,8,9,10,11,13,14,16,17,18,19,20,21].…”

Section: Q4mentioning

confidence: 99%

Study of the monte–carlo fault injection simulator to measure a fault derating

Lee

2019

IET Computers & Digital Techniques

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“…In our view, the designer of a new queuemanagement algorithm would be better off accessing these primitives through a high-level procedural language, such as C++, through the Verilog Procedural Interface [8].…”

Section: What Interface Should the Switch Expose?mentioning

confidence: 99%

No silver bullet

Sivaraman

Winstein

Subramanian

et al. 2013

Proceedings of the Twelfth ACM Workshop on Hot Topics in Networks

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The data plane is in a continuous state of flux. Every few months, researchers publish the design of a new highperformance queueing or scheduling scheme that runs inside the network fabric. Many such schemes have been queen for a day, only to be surpassed soon after as methods -or evaluation metrics -evolve.The lesson, in our view: there will never be a conclusive victor to govern queue management and scheduling inside network hardware. We provide quantitative evidence by demonstrating bidirectional cyclic preferences among three popular contemporary AQM and scheduling configurations.We argue that the way forward requires carefully extending Software-Defined Networking to control the fast-path scheduling and queueing behavior of a switch. To this end, we propose adding a small FPGA to switches. We have synthesized, placed, and routed hardware implementations of CoDel and RED. These schemes require only a few thousand FPGA "slices" to run at 10 Gbps or more -a minuscule fraction of current low-end FPGAs -demonstrating the feasibility and economy of our approach.

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“…While the µarch-level simulator can access the named pipes like files, the gate-level simulator is enhanced with two system tasks, implemented using the Verilog Procedural Interface (VPI) [9], that handle accesses to/from the pipes: One collects signals from the stimuli pipe and the other writes the results to the response pipe. The stimuli and response (arguments of the two tasks) are tailored to the µarch-level structures under fault injection.…”

Section: Interfacing the Simulatorsmentioning

confidence: 99%