The Ultrascalar processor-an asymptotically scalable superscalar microarchitecture

Henry, Dana S.; Kuszmaul, Bradley C.; Viswanath, Vinod

doi:10.1109/arvlsi.1999.756053

Cited by 9 publications

(6 citation statements)

References 20 publications

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“…To eliminate the power overheads that are inherent in conventional out of order processors, we sought inspiration from an unlikely source: the Ultrascalar microarchitecture [38], a massively wide 64issue design that was proposed during the heyday of high-ILP Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.…”

Section: In Place Execution In Cribmentioning

confidence: 99%

“…Inspired by the Ultrascalar proposal [38], instructions are executed in place at distributed execution stations that consolidate renaming, issue logic, and bypassing in a single CRIB structure. As shown in Figure 1, the execution and communication resources are laid out in two dimensions, placing logical register names in horizontally-spaced columns and instructions ascending vertically in program order.…”

Section: Introductionmentioning

confidence: 99%

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Gunadi

Lipasti

2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

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Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined execution lanes. This requires multiple complex structures and repeated dependency resolution, imposing a significant dynamic power overhead. This paper advocates in-place execution of instructions, a power-saving, pipeline-free approach that consolidates rename, issue, and bypass logic into one structure-the CRIB-while simultaneously eliminating the need for a multiported register file, instead storing architected state in a simple rank of latches. CRIB achieves the high IPC of an out-of-order machine while keeping the execution core clean, simple, and low power. The datapath within a CRIB structure is purely combinational, eliminating most of the clocked elements in the core while keeping a fully synchronous yet high-frequency design. Experimental results match the IPC and cycle time of a baseline outof-order design while reducing dynamic energy consumption by more than 60% in affected structures.

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Section: In Place Execution In Cribmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Crib

Gunadi

Lipasti

2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

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“…One problem with a non-wrap-around scheduler on a wrap-around window is that it can exhibit non-monotonic behavior. 3 It can be very difficult to write good compilers for processors that exhibit non-monotonic behavior.…”

Section: Our Simulation Environmentmentioning

confidence: 99%

“…This work was partly motivated by our previous theoretical results on asymptotically optimal superscalar processors [3,6]. In contrast, this work focuses on understanding the engineering problems of the wide-issue processors of the near future.…”

Section: Introductionmentioning

confidence: 98%

Circuits for wide-window superscalar processors

Henry

Kuszmaul

Loh

et al. 2000

SIGARCH Comput. Archit. News

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Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor implemented in today's technology can achieve an increase of 10-60% (geometric mean of 31%) in program speed compared to today's processors. The processor operates at clock speeds comparable to today's processors, but achieves significantly higher ILP.To measure the impact of a large window on clock speed, we design and simulate new implementations of the logic components that most limit the critical path of our large-window processor: the schedule logic and the wake-up logic. We use log-depth cyclic segmented prefix (CSP) circuits to reimplement these components. Our layouts and simulations of critical paths through these circuits indicate that our large-window processor could be clocked at frequencies exceeding 500MHz in today's technology. Our commit logic and rename logic can also run at these speeds.To measure the impact of a large window on ILP, we compare two microarchitectures, the first has a 128-instruction window, an 8-wide fetch unit, and 20-wide issue (four integer, branch, multiply, float, and memory units), whereas the second has a 32-instruction window, and a 4-wide fetch unit and is comparable to today's processors. For each, we simulate different window reuse and bypass policies. Our simulations show that the large-window processor achieves significantly higher IPC. This performance increase comes despite the fact that the large-window processor uses a wrap-around window while the small-window processor uses a compressing window, thus effectively increasing its number of outstanding instructions. Furthermore, the large-window processor sometimes pays an extra clock cycle for bypassing.

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“…The register file itself must be modeled as a hierarchy. (In this general vein, an interesting study of the scalability of a superscalar RISC processor with respect to the size of the instruction window is developed in [20].) Rather than pursuing this approach, we explore a different instruction execution mechanism, which circumvents the problem.…”

Section: The Sport Computer and The Ph-ram Modelmentioning

confidence: 99%

Optimal organizations for pipelined hierarchical memories

Bilardi

Ekanadham

Pattnaik

2002

Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures

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In a recent paper (SPAA'01), we have established that the Pipelined Hierarchical Random Access Machine (PH-RAM) is a powerful model of computation, where most of the memory latency can be hidden by concurrency of accesses. In the present work, we explore the physical feasibility of PH-RAMs.A pipelined hierarchical memory of size S is characterized by two metrics: the access function a(x), denoting the time required by an access to location x, and the pipeline period p(S), denoting the minimum time between subsequent accesses that can be sustained. Physical constraints on minimum device size and maximum signal speed imply that, for a memory laid out in d dimensions, a(x) = Ω(x 1/d ). We propose a novel memory organization scheme that can be specialized to yield optimal performance a(x) = O(x 1/d ) and p(S) = O(1), for any d ≥ 1.Managing a large number of concurrent load and store instructions would pose a significant burden on a traditional RISC processor, requiring both a large register file and complex logic to properly synchronize instructions. We show how these obstacles can be circumvented by introducing the Scalable transPORT (SPORT) computer where a simple processor drives a version of our pipelined hierarchical memory capable of servicing memory-to-memory instructions. We show that SPORT provides a feasible, scalable implementation of the PH-RAM model.

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The Ultrascalar processor-an asymptotically scalable superscalar microarchitecture

Cited by 9 publications

References 20 publications

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Circuits for wide-window superscalar processors

Optimal organizations for pipelined hierarchical memories

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