Circuits for wide-window superscalar processors

Abstract

Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor implemented in today's technology can achieve an increase of 10-60% (geometric mean of 31%) in program speed compared to today's processors. The processor operates at clock speeds comparable to today's processors, but achieves significantly higher ILP.To measure the impact of a large window on clock speed, we design and simulate new implementations of the logic components that most limit the critical path of our large-window processor: the schedule logic and the wake-up logic. We use log-depth cyclic segmented prefix (CSP) circuits to reimplement these components. Our layouts and simulations of critical paths through these circuits indicate that our large-window processor could be clocked at frequencies exceeding 500MHz in today's technology. Our commit logic and rename logic can also run at these speeds.To measure the impact of a large window on ILP, we compare two microarchitectures, the first has a 128-instruction window, an 8-wide fetch unit, and 20-wide issue (four integer, branch, multiply, float, and memory units), whereas the second has a 32-instruction window, and a 4-wide fetch unit and is comparable to today's processors. For each, we simulate different window reuse and bypass policies. Our simulations show that the large-window processor achieves significantly higher IPC. This performance increase comes despite the fact that the large-window processor uses a wrap-around window while the small-window processor uses a compressing window, thus effectively increasing its number of outstanding instructions. Furthermore, the large-window processor sometimes pays an extra clock cycle for bypassing.

Arbitrate-and-move primitives for high throughput on-chip interconnection networks

“…Furthermore the proposed an arbitration scheme may prove useful in areas where performance is held back due to high latency of present arbitration and scheduling schemes, such as issue-logic of wideissue superscalar processors [3].…”

Data-flow prescheduling for large instruction windows in out-of-order processors

“…A circuit-level approach was proposed recently for tackling the window size problem specifically [5] : the reorder buffer and the issue buffer are merged, and parallel-prefix circuits are used for the wake-up and selection phases.…”

Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions

“…From Figure 1, we observe that, while the negative effects of out-oforder execution existed for only a small fraction of the time with small reorder buffers, eliminating other sources of stalls by increasing the out-of-order capability exposes these negative effects to represent significant overhead. Since recent research and industry trends are focusing on increasing out-of-order capability [4,5,11,13,16,18,20,24], with the results from Figure 1 in mind, we believe it is imperative that the frequency of traps and the number of cache misses be reduced so that future high performance processors can realize the full potential of more complex out-of-order designs.…”

“…A good deal of recent effort is aimed at designing efficient and fast issue/selection logic that allows for larger instruction-window sizes while still maintaining high clock speeds. Henry et al proposed an alternate binary tree circuit implementation for the wakeup logic [11]; Onder et al proposed explicit wake-up lists associated with executing instructions [16]; Lebeck et al tackle the instruction window size by proposing an alternate waiting instruction buffer (WIB) [13]; and Akkary et al propose a checkpoint and recovery mechanism to recover from branch mispredicts with larger instruction window sizes [4].…”

“…Previous studies have shown that increasing the size of reorder buffers, issue queues, and load/store queues can lead to increased performance [4,13,16,18,20]; consequently, much research has looked at the feasibility of increasing the size of these hardware data structures without negatively impacting clock cycle time [5,11,13]. However, when one considers "real" effects due to the reordering of memory instructions, the potential performance gains largely disappear.…”