The turn model for adaptive routing

Glass, Christopher J.; Ni, Lionel M.

doi:10.1145/285930.286003

Cited by 235 publications

(411 citation statements)

References 9 publications

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“…Here, a turn is deÞned as a speciÞc pair of input-output links around a node [12]. The main claim is that in order to break all the cycles in a network, it is sufÞcient to prohibit a set of turns instead of a set of links, as is the case with spanning trees (a turn´ µ around some node is prohibited if not packets can be forwarded from link´ µ to link´ µ).…”

Section: Introductionmentioning

confidence: 99%

Application of network calculus to general topologies using turn-prohibition

Starobinski

Karpovsky

Zakrevski

2003

IEEE/ACM Trans. Networking

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Abstract-Network calculus is known to apply in general only to feed-forward routing networks, i.e., networks where routes do not create cycles of interdependent packet flows. In this paper, we address the problem of using network calculus in networks of arbitrary topology. For this purpose, we introduce a novel graph-theoretic algorithm, called turn-prohibition (TP), that breaks all the cycles in a network and, thus, prevents any interdependence between flows. We prove that the TP-algorithm prohibits the use of at most 1/3 of the total number turns in a network, for any network topology. Using analysis and simulation, we show that the TP-algorithm significantly outperforms other approaches for breaking cycles, such as the spanning tree and up/down routing algorithms, in terms of network utilization and delay bounds. Our simulation results also show that the network utilization achieved with the TP-algorithm is within a factor of two of the maximum theoretical network utilization, for networks of up to 50 nodes of degree four. Thus, in many practical cases, the restriction of network calculus to feed-forward routing networks may not represent a too significant limitation.

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Section: Introductionmentioning

confidence: 99%

Application of network calculus to general topologies using turn-prohibition

Starobinski

Karpovsky

Zakrevski

2003

IEEE/ACM Trans. Networking

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“…This is the case of XY , SR h , and U D. Other routing algorithms like FX [10] and Turn Model [5] also adhere to these conditions, thus being suitable for LBDR. Figure 3.a shows the details of LBDR.…”

Section: System Environmentmentioning

confidence: 99%

Logic-Based Distributed Routing for NoCs

Flich

Duato

2008

IEEE Comput. Arch. Lett.

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Abstract-The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are usually proposed for NoCs, heterogeneous cores, manufacturing defects, hard failures, and chip virtualization may lead to irregular topologies. In this context, efficient routing becomes a challenge. Although switches can be easily configured to support most routing algorithms and topologies by using routing tables, this solution does not scale in terms of latency and area.We propose a new circuit that removes the need for using routing tables. The new mechanism, referred to as Logic-Based Distributed Routing (LBDR), enables the implementation in NoCs of many routing algorithms for most of the practical topologies we might find in the near future in a multicore chip. From an initial topology and routing algorithm, a set of three bits per switch output port is computed. By using a small logic block, LBDR mimics (demonstrated by evaluation) the behavior of routing algorithms implemented with routing tables. This result is achieved both in regular and irregular topologies. Therefore, LBDR removes the need for using routing tables for distributed routing, thus enabling flexible, fast and power-efficient routing in NoCs.

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“…Under realistic traffic patterns which pose the problem of hotspot traffic congestion areas, XY deterministic routing failed to avoid hotspots and resulted in high-average latencies [36]. Adaptive routing guides the router to react to hotspots created by different traffic patterns, by allowing a packet at the input buffer to request more than one output port or direction [37]. While minimal routing algorithms prevent livelock from occurring, adaptive routing introduces the possibility of deadlock, which can be prevented by applying odd-even turn model restrictions to the routing decision [38].…”

Section: State Of the Artmentioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2012

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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The turn model for adaptive routing

Cited by 235 publications

References 9 publications

Application of network calculus to general topologies using turn-prohibition

Application of network calculus to general topologies using turn-prohibition

Logic-Based Distributed Routing for NoCs

Networks on Chips: Structure and Design Methodologies

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