The Transition to Chip-level Optical Interconnects

Haney, Michael W.; Sparacin, Daniel K.; Hodiak, J.H.

doi:10.1364/ofc.2010.omv2

Cited by 3 publications

(5 citation statements)

References 4 publications

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“…Achieving this will require chip I/O levels that scale with on-chip processing power [13]. As shown in Figure 3, this will require chip-scale signaling in the ~100's fJ/bit range, which is beyond the capabilities of current metal trace based signaling technology.…”

Section: Example: Pics For Integrated Chip-scale Computer Interconnectsmentioning

confidence: 99%

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How will photonic integrated circuits develop?

Haney

2013

SPIE Proceedings

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This paper explores issues associated with Photonic Integrated Circuit (PIC) research and development -with an overall goal of initiating a discussion of how PIC technology should develop and eventually be deployed with high impact. Significant research and development programs have focused on PICs for routing and switching, and computer interconnects. Most recently, the application domain of PICs has diversified greatly, and now includes analog signal processing, remote sensing, biological and chemical sensing, neural interfacing, and solar cells. A key feature of PIC technology growth has been the exploitation of high-density fabrication and packaging technology originally developed for the Silicon IC industry. PIC foundry services are emerging -and there has been a natural attempt to ascribe a "Moore's Law" to PIC scaling. Analogies to Silicon electronic scaling, however, should be used with caution. PIC complexity scaling may be driven more by the ability to access the degrees-of-freedom offered by PIC-based optical domain signal processing, rather than increasing device count. Specific examples of PIC research in chip-scale computer interconnects and integrated micro-concentrators for solar cells are highlighted.Much research and development has been, and is currently, focused on applying photonic integrated circuits (PICs) to chip-scale digital optical interconnects (OI) for high-density, high-throughput, computer communications [1-8] and networking [9]. In OI there is a specific goal of overcoming the performance limits of high-density metal interconnects and there has been an emphasis on developing monolithically integrated Silicon Photonic platforms to exploit the fabrication precision and device densities associated with Silicon ICs, as well as the potential for tight integration with Silicon electronic circuits. However, as evidenced by recent initiatives at the Defense Advanced Research Projects Agency (DARPA) and other sponsoring agencies, the PIC application domain may expand well beyond OI. The diverse application domain being considered for PICs now ranges from analog signal processing, to routing, to remote sensing, to biological sensing, to solar cells. This widening application domain will likely entail exploitation of a diverse set of technology platforms to match to the particular demands of processing and interfacing for each application. One can imagine a set of application-specific platforms optimized to address the particular performance requirements. One common challenge for all applications will center on engineering the interface between the PIC and optical energy that it exploits -be it for sensing, signal processing, computing, actuation, or energy transduction. Given this focus on optimizing the interface, it is anticipated that PICs will often involve hybrid integration and packaging of differing technologies. Such efforts should be able to leverage the advances made in Silicon IC packaging. Figure 1 depicts the expanding application domain of PIC technology as a pie-shaped chart. ...

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Section: Example: Pics For Integrated Chip-scale Computer Interconnectsmentioning

confidence: 99%

“…(adapted from[13]). Modern HPC systems maintain roughly constant FLOPS/W performance across several orders-of-magnitude in computational throughput as shown by red diamonds corresponding to systems in the 2010 timeframe.…”

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confidence: 99%

How will photonic integrated circuits develop?

Haney

2013

SPIE Proceedings

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“…This results in estimated requirements of 5mW/Gbps and $0.17/Gbps in 2016 when 4x10 7 optical links will be required per super computer, versus just 48000 in 2008. 4 This large number of parallel channels will also require a commensurate increase in per channel reliability, in order to maintain overall system reliability levels.…”

Section: Areas Of Importance For Future Data Communication Transceivementioning

confidence: 99%

“…Future high-performance commercial and military computing architectures are projected to require 10's, and conceivably even 100's, of TB/s of bandwidth to the chip. 6,7 Current component cost is $2-$2.5/Gbps and power consumption is ~20-25mW/Gbps. Clearly a significant improvement is required at both the component and system level to meet these targets.…”

Section: Areas Of Importance For Future Data Communication Transceivementioning

confidence: 99%

Advantages of CMOS photonics for future transceiver applications

Guckenberger¹,

Abdalla²,

Bradbury³

et al. 2010

36th European Conference and Exhibition on Optical Communication

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“…The communication bottleneck and energy consumption per bit at the chip-level are major limitations to the performance of microprocessors [2,3]. For intra-chip communications, this is particularly evident in global interconnects which connect remote parts of the chip.…”

Section: Introductionmentioning

confidence: 99%