The Study of the Device Performance of the Hetero-junction Vertical Trench MOSFET

Liao, Yulong; Feng, Ke; Li, Ping; Peng, Chenxi; Nie, Ruihong; Li, Yaosen; Xiong, Xuanlin

doi:10.1109/icet51757.2021.9451090

Cited by 1 publication

(1 citation statement)

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“…It is also reported that, for the process beyond (less than) 2 nm, the vertical structure may further reduce power consumption and chip area compared with the lateral transfer devices [5]. At this moment, we proposed a Hetero-junction Vertical Trench MOSFET (HVTFET) structure with independent intellectual property rights [6] and carried out a lot of simulation research on it [7]. The HVTFET structure is somehow similar to the FinFET and the GAAFET in terms of 3D IC, however, their operating principles are quite different.…”

Section: Introductionmentioning

confidence: 99%

The Research on the Fabrication of the Novel Basic Unit for 3D Structure Integrated Circuit

Liao

et al. 2023

J. Phys.: Conf. Ser.

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The IC industry in the Chinese mainland has encountered the difficulty caused by the embargo on lithography machines in developing state-of-the-art semiconductor IC processes. For the first time, this work fabricates out the HVTFET which we have independent intellectual property rights. A 50 nm channel length N HVTFET device is fabricated successfully using a 0.35 µm process, and its characteristics are close to those of TSMC’s 55 nm planar N MOSFET. The experimental results of this paper have two important significances. First, it shows that the fabrication of the advanced ICs in the Chinese mainland can get rid of the limitation of the lithography machine by using the HVTFET. Second, it shows that it is possible to decrease the chip area by about 3/4 by using the HVTFET structure for the ICs with 28 nm and above planar MOS processes, which are quite common in China.

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Section: Introductionmentioning

confidence: 99%