The structure of chips and links comprising the IBM eServer z990 I/O subsystem

With the introduction of the high-frequency IBM System z10e processor design, a new, robust cache hierarchy was needed to enable up to 80 of these processors aggregated into a tightly coupled symmetric multiprocessor (SMP) system to reach their performance potential. Typically, each time the processor frequency increases by a significant factor, as did the z10e processor over the predecessor IBM System z9t processor, the access time of data, as measured by the number of processor cycles beyond the level 1 cache on an identical processor cache subsystem, would increase proportionally as well because the flight time on the chip interconnects across multiple hardware packaging levels has stayed relatively constant in nanoseconds. To address the latency scaling problem and the increased demand of the larger 80-way SMP size, the z10 processor cache subsystem introduces new innovative concepts and solutions.

Section: I/o Subsystemmentioning

confidence: 99%

IBM System z10 processor cache subsystem microarchitecture

Mak¹,

Walters²,

Strait³

2009

“…More complete information on I/O chips and the STI network can be found in [2,7,8]. Changes to the hardware that were required in order to make RII possible are described in subsequent sections of this paper.…”

Section: Overviewmentioning

confidence: 99%

Redundant I/O interconnect

Helmich

Becht

Easton³

et al. 2007

Self Cite

The outstanding reliability, availability, and serviceability (RAS) characteristics of IBM mainframe computers are among the features that gained the IBM eServere family its reputation as a leading platform for business-critical applications. The aim now is to further improve IBM System z9t RAS by introducing redundant I/O interconnect (RII) as a building block of enhanced book availability and recovery scenarios. RII provides a means of maintaining I/O connectivity during planned or unplanned outages in a way that is transparent to the operating system and customer applications. The mechanism that meets this requirement is the provision of an alternate path to the I/O cage, which provides highbandwidth I/O slots to enable a higher number of I/O ports per card. This paper discusses the I/O subsystem hardware and firmware aspects of RII.

“…The STI switch chip provides high-speed connections between the memory bus adapter (MBA) and the I/O attachments [2] and to other systems within the Parallel Sysplex* [3]. The switch chip is also called the multiplexor/ demultiplexor chip.…”

Section: Introductionmentioning

confidence: 99%

Functional verification of a frequency-programmable switch chip with asynchronous clock sections

Hoppe

Arthur-Mensah²,

Chencinski³

et al. 2004

Self Cite

An integral part of the IBM eServer z990 I/O subsystem is the self-timed interface (STI) switch chip. The STI switch is an application-specific integrated circuit (ASIC) designed to provide high I/O connectivity and high bandwidth within the system. The complexity of the functional verification of the STI switch chip is inherent in the implementation of seventeen logical clock domains and the support of six different STI interfaces with programmable frequencies. The logic within these clock domains is connected via asynchronous interfaces. This paper describes the methodology to verify the functionality of the switch chip with various STIs by introducing a combination of verification techniques. This involves random biased stimulus generation, automated result prediction checking, and the use of cycle simulation to stress the logical design. The cycle simulation required new techniques to model equivalent behavior in order to verify the correct integration of nondigital components on the chip. Advanced methods were implemented to ensure correctness of the frequency-dependent design units and functionality across the asynchronous interfaces. A single verification environment was developed, providing the flexibility to seamlessly support the different levels of design abstraction and uncover the design errors at the appropriate level.