IBM System z10 processor cache subsystem microarchitecture

Mak, P.; Walters, C. R.; Strait, G. E.

doi:10.1147/jrd.2009.5388579

Cited by 9 publications

(4 citation statements)

References 7 publications

(12 reference statements)

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“…Read-only-XIs are sent to caches that own the line read-only; no response is needed for such XIs since they cannot be rejected. The details of the SMP protocol are very similar to those described for the IBM z10 in [21].…”

Section: A System Backgroundmentioning

confidence: 99%

Transactional Memory Architecture and Implementation for IBM System Z

Jacobi¹,

Slegel²,

Greiner

2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

121

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We present the introduction of transactional memory into the next generation IBM System z CPU. We first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure. We explain practical reasons behind our choices. The zEC12 system is available since September 2012.

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Section: A System Backgroundmentioning

confidence: 99%

Transactional Memory Architecture and Implementation for IBM System Z

Jacobi¹,

Slegel²,

Greiner

2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

121

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“…-Stores account for a majority of data cache directory misses [14] in all SPECjvm2008 benchmarks. This is unexpected because the load-to-store ratio in programs is typically on the order of 5:1.…”

Section: Opportunities Discoveredmentioning

confidence: 99%

Mining Opportunities for Code Improvement in a Just-In-Time Compiler

Jocksch

Mitran

Siu

et al. 2010

Lecture Notes in Computer Science

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Abstract. The productivity of a compiler development team depends on its ability not only to the design effective solutions to known code generation problems, but also to uncover potential code improvement opportunities. This paper describes a data mining tool that can be used to identify such opportunities based on a combination of hardware-profiling data and on compiler-generated counters. This data is combined into an Execution Flow Graph (EFG) and then FlowGSP, a new data mining algorithm, finds sequences of attributes associated with subpaths of the EFG. Many examples of important opportunities for code improvement in the IBM R Testarossa compiler are described to illustrate the usefulness of this data mining technique. This mining tool is specially useful for programs whose execution is not dominated by a small set of frequently executed loops. Information about the amount of space and time required to run the mining tool are also provided. In comparison with manual search through the data, the mining tool saved a significant amount of compiler development time and effort.

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“…Together, these features enable the platform to better support the traditional Large Systems Performance Reference (LSPR) workload set, to better utilize the hardware/software synergy that emerged on the preceding z10 platform, and to provide a highly competitive platform for emerging workloads while continuing the trend for increased box capacity within a constant energy footprint from one generation to the next. The sections that follow contain a comparative analysis between the z196 platform and its predecessor z10 platform [2,3].…”

Section: Introductionmentioning

confidence: 99%

IBM zEnterprise 196 microprocessor and cache subsystem

Busaba¹,

Blake²,

Curran³

et al. 2012

IBM J. Res. & Dev.

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The IBM zEnterprise A 196 (z196) system, announced in the second quarter of 2010, is the latest generation of the IBM System z A mainframe. The system is designed with a new microprocessor and memory subsystems, which distinguishes it from its z10 A predecessor. The system has up to 40% improvement in performance for traditional z/OS A workloads and carries up to 60% more capacity when compared with its z10 predecessor. The memory subsystem has four levels of cache hierarchy (L1 through L4) and constructs the L3 and L4 caches with embedded DRAM silicon technology, which achieves approximately three times the cache density over traditional static RAM technology. The microprocessor has 50% more decode and dispatch bandwidth when compared with the z10 microprocessor, as well as an out-of-order design that can issue and execute up to five instructions every single cycle. The microprocessor has an advanced branch prediction structure and employs enhanced store queue management algorithms. At the date of product announcement, the microprocessor was the fastest complex-instruction-set computing processor in the industry, running at a sustained 5.2 GHz, executing approximately 1,100 instructions, 220 of which are cracked into reduced-instruction-set computing-type operations, to achieve large performance gains in legacy online transaction processing and compute-intensive workloads.

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IBM System z10 processor cache subsystem microarchitecture

Cited by 9 publications

References 7 publications

Transactional Memory Architecture and Implementation for IBM System Z

Transactional Memory Architecture and Implementation for IBM System Z

Mining Opportunities for Code Improvement in a Just-In-Time Compiler

IBM zEnterprise 196 microprocessor and cache subsystem

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