The Spallation neutron source accelerator low level RF control system

Abstract

The Spallation Neutron Source Low Level RF Team includes members from Lawrence Berkeley, Los Alamos, and Oak Ridge national laboratories. The Team is responsible for the development, fabrication and commissioning of 98 Low Level RF (LLRF) control systems for maintaining RF amplitude and phase control in the Front End (FE), Linac and High Energy Beam Transport (HEBT) sections of the SNS accelerator, a 1 GeV, 1.4 MW proton source. The RF structures include a radio frequency quadrupole (RFQ), rebuncher cavities, and a drift tube linac (DTL), all operatingat 402.5 MHz, and a coupled-cavity linac (CCL), superconducting linac (SCL), energy spreader, and energy corrector, all operating at 805 MHz. The RF power sources vary from 20 kW tetrode amplifiers to 5 MW klystrons. A single control system design that can be used throughout the accelerator is under development and will begin deployment in February 2004. This design expands on the initial control systems that are currently deployed on the RFQ, rebuncher and DTL cavities. An overview of the SNS LLRF Control System is presented along with recent test results and new developments.

Decoupling PI controller design for a normal conducting RF cavity using a recursive LEVENBERG-MARQUARDT algorithm

“…When beam is not loaded, the transfer matrix (12) of the openloop system is expressed as a generic form (14) ( 15) In order to identify the open-loop system, the step response test [6], [9] is applied. Since the system is TITO, two step response tests are performed.…”

“…Note that the above method for identifying the steady-state gain matrix can be applied for any input pairs guaranteeing nonsingularity of the matrix . The step response of (14) to is given by Consider the first equation. Integrating both side of the first equation with respect to , we obtain…”

“…The operating frequency of DTL1 is 402.5 MHz and with the 352.5-MHz IF frequency, the 50-MHz LO signal is obtained, and a direct demodulation at 40 MHz is applied. From this, we obtain baseband signal samples and signal samples at a sample frequency 10 MHz [12]- [14]. The 10-MHz and signals are stored in buffers.…”

“…The 10-MHz and signals are stored in buffers. However, due to the limitation of a physical memory size in digital front end (DFE) system implemented with FPGA [14], [15], the and signal samples are down sampled. The current version DFE provides 256 data points for every 1 ms long pulse.…”

Digital Low-Level RF Conctrols for Future Superconducting Linear Colliders

“…More complex algorithm are implemented on slower floating point DSPs such as the C6701 from Texas Instruments or the Sharc from Analog Devices. Typical configurations of the digital feedback hardware can are documented in [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15].…”