The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory

Flash memory cells-an overview

“…Moreover, when charge is injected from the polysilicon FG, the number of poly grains in the tunneling area plays an important role in determining the distribution width [71].…”

Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

“…9(a) shows a family of FN tunneling currents. In each I G curve, (8) was solved numerically with given erase time of t e = 10 ms, obtaining V FGe . In generating a family of I G curves, C T was randomly varied around its target value to simulate the I G s at different memory cells.…”

“…The total distribution can also be calculated directly from (8), (9), and (12) by randomly varying the parameters simultaneously. Now, that ∆V Te has been specified via the random variations of cell parameters, the next task is to discuss the origins of such variation.…”

“…The change of V TFG due to ∆T OX is same for both process types. With I G , C TNL , and V TFG thus obtained, the erase V T was calculated by using (8), (9), and (12). The common parameters used for calculation are:…”

“…V T dispersion in small cells is more sensitively affected by local effects such as the discrete dopant fluctuation [4]- [7], random polysilicon grain size [8], etc., Also, because of the high packing density the interference between adjacent cells results in further V T shifts [9]. Recently, the control of the edgeprofile of the tunnel oxide in 90-nm NOR Flash memory cells was shown to improve V T distribution [10], [11], indicating that the edge geometry also affects V T .…”