The Smallest ARIA Module with 16-Bit Architecture

Yang, Shanlin; Park, Jinsub; You, Younggap

doi:10.1007/11927587_11

Cited by 6 publications

(8 citation statements)

References 8 publications

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“…However, the proposed architectures of 32-bit and 16-bit are more efficient within throughput as shown in Table 6. Our non-masked ARIA, which is composed with the proposed 8/16-bit structure, is relatively larger than a previous work [12]. That is, the previous work [12] has latches for memory.…”

Section: Implementation Results and Performance Evaluationmentioning

confidence: 99%

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Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

Kang¹,

Choi²,

Choi³

et al. 2012

ETRI J

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The block cipher ARIA has been threatened by sidechannel analysis, and much research on countermeasures of this attack has also been produced. However, studies on countermeasures of ARIA are focused on software implementation, and there are no reports about hardware designs and their performance evaluation. Therefore, this article presents an advanced masking algorithm which is strong against second-order differential power analysis (SODPA) and implements a secure ARIA hardware. As there is no comparable report, the proposed masking algorithm used in our hardware module is evaluated using a comparison result of software implementations. Furthermore, we implement the proposed algorithm in three types of hardware architectures and compare them. The smallest module is 10,740 gates in size and consumes an average of 47.47 μW in power consumption. Finally, we make ASIC chips with the proposed design, and then perform security verification. As a result, the proposed module is small, energy efficient, and secure against SODPA.

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Section: Implementation Results and Performance Evaluationmentioning

confidence: 99%

“…Our non-masked ARIA, which is composed with the proposed 8/16-bit structure, is relatively larger than a previous work [12]. That is, the previous work [12] has latches for memory. It is hard to reduce the size of ARIA modules because of memories in fact.…”

Section: Implementation Results and Performance Evaluationmentioning

confidence: 99%

Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

Kang¹,

Choi²,

Choi³

et al. 2012

ETRI J

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show abstract

“…However, only a small number of papers have been published on the hardware architecture for the ARIA algorithm in contrast to AES. A compact design of ARIA was proposed in two recent studies [10], [11]. In particular, [11] suggested a 16-bit architecture of ARIA and proposed a substitution block that used composite field arithmetic.…”

Section: Related Workmentioning

confidence: 99%

“…A compact design of ARIA was proposed in two recent studies [10], [11]. In particular, [11] suggested a 16-bit architecture of ARIA and proposed a substitution block that used composite field arithmetic. An implementation of a unified hardware architecture for ARIA and AES was reported in [12].…”

Section: Related Workmentioning

confidence: 99%

“…An effort was made to explain the detailed matrix conversion, following the affine transformation equations, and the merged matrix of the affine transformation with an isomorphic function between GF(2 8 ) and GF(2 4 ) 2 . Such an elaborate description was omitted in two earlier studies [11], [12], although it is very important for further improvements.…”

Section: Contributionmentioning

confidence: 99%

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High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

2008

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This paper presents two types of high‐speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area‐throughput trade‐offs are evaluated depending on the S‐box implementation by using look‐up tables or combinational logic which involves composite field arithmetic. The sub‐pipelined architectures for non‐feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S‐box implementation using composite field arithmetic over GF(24)2, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 μm CMOS technology. This is the first sub‐pipelined architecture of ARIA for high throughput to date.

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Design and fabrication of antireflective nanoparticulate thin films with superhydrophilic self-cleaning properties on glass substrate

Lin

et al. 2011

Journal of the Taiwan Institute of Chemical Engineers

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The Smallest ARIA Module with 16-Bit Architecture

Cited by 6 publications

References 8 publications

Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

Design and fabrication of antireflective nanoparticulate thin films with superhydrophilic self-cleaning properties on glass substrate

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