High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

Lee, Sang Woo; Moon, SangJae; Kim, Jeong-Nyeo

doi:10.4218/etrij.08.0108.0194

Cited by 4 publications

(5 citation statements)

References 28 publications

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“…When we compare our 128-bit masked ARIA module to non-masked ARIA [6], the proposed masking module has low throughput. However, the proposed architectures of 32-bit and 16-bit are more efficient within throughput as shown in Table 6.…”

Section: Implementation Results and Performance Evaluationmentioning

confidence: 99%

“…Thus, S-boxes in the ARIA can be described as where x -1 is the inversion function over GF (2 8 ), and A, B, D, and D -1 are 8×8 binary matrices for affine transform. The matrix A and D are defined in [6]. The diffusion layer of ARIA is originally represented by a multiplication of the 16×16 involution matrix C with a 16×1 input vector I=(I 0 , I 1 , …, I 15 ) T ; therefore, the diffusion output can be denoted as O = C·I [7].…”

Section: Previous Work 1 Block Cipher Ariamentioning

confidence: 99%

“…Although there is much research on the ARIA hardware modules which do not include masking and the related architectures [6], [11]- [13], there are no studies on comparison of efficiency and structures for masked ARIA hardware implementation. In this section, we describe the masked hardware architectures considering previous architectures, implement the proposed algorithm to hardware modules, and compare the designs.…”

Section: Adaptive Random Masking H/w Implementationmentioning

confidence: 99%

See 2 more Smart Citations

Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

Kang¹,

Choi²,

Choi³

et al. 2012

ETRI J

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The block cipher ARIA has been threatened by sidechannel analysis, and much research on countermeasures of this attack has also been produced. However, studies on countermeasures of ARIA are focused on software implementation, and there are no reports about hardware designs and their performance evaluation. Therefore, this article presents an advanced masking algorithm which is strong against second-order differential power analysis (SODPA) and implements a secure ARIA hardware. As there is no comparable report, the proposed masking algorithm used in our hardware module is evaluated using a comparison result of software implementations. Furthermore, we implement the proposed algorithm in three types of hardware architectures and compare them. The smallest module is 10,740 gates in size and consumes an average of 47.47 μW in power consumption. Finally, we make ASIC chips with the proposed design, and then perform security verification. As a result, the proposed module is small, energy efficient, and secure against SODPA.

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Section: Implementation Results and Performance Evaluationmentioning

confidence: 99%

Section: Previous Work 1 Block Cipher Ariamentioning

confidence: 99%

Section: Adaptive Random Masking H/w Implementationmentioning

confidence: 99%

See 1 more Smart Citation

Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

Kang¹,

Choi²,

Choi³

et al. 2012

ETRI J

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show abstract

“…In order to ensure specialized security in cryptography environment, [8] suggested the work of a intermediate approach to introduce a trusted third party. A trust-overlay network [9] provides multiple data units for performing a reputation coding of trust between service providers and data source. An article describing the features of security coding is outlined in [10,11].…”

Section: Introductionmentioning

confidence: 99%

Resource Optimized Security Coding In Light Weight Security Protocol

Tappari¹,

Sridevi²

2019

IJITEE

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The overhead for resource utilization in the round coding operation of security coding is large. Though lightweight protocols are used as a measure of provisioning, higher level of security in many real time applications, the need of key scheduling, key generation and s-box operation leads to large resource utilization. This resource consumption intern leads to large power consumption and area overhead. To minimize the resource utilization in this paper, a new resource optimization technique following resource reutilization scheme is proposed. The resource utilization is synchronized by the delay term instruction application in cryptography coding.

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“…The combinational design of the proposed Information 2018, 9, 13 2 of 14 lightweight S-box offers hardware advantages-namely compactness in terms of a smaller number of gates-enables sub-pipelining to improve performance optimization and also enables masking mechanisms to counteract side channel attacks [11]. Hardware implementations of the symmetric cryptographic algorithms have been widely explored in the literature [12][13][14][15][16][17]. However, they report the bare minimal focus on the architectural design of the different symmetric lightweight security ciphers.…”

Section: Introductionmentioning

confidence: 99%

Lightweight S-Box Architecture for Secure Internet of Things

Prathiba

Bhaaskaran

2018

Information

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Lightweight cryptographic solutions are required to guarantee the security of Internet of Things (IoT) pervasiveness. Cryptographic primitives mandate a non-linear operation. The design of a lightweight, secure, non-linear 4 × 4 substitution box (S-box) suited to Internet of Things (IoT) applications is proposed in this work. The structure of the 4 × 4 S-box is devised in the finite fields GF (2 4 ) and GF ( (2 2 ) 2 ). The finite field S-box is realized by multiplicative inversion followed by an affine transformation. The multiplicative inverse architecture employs Euclidean algorithm for inversion in the composite field GF ( (2 2 ) 2 ). The affine transformation is carried out in the field GF (2 4 ). The isomorphic mapping between the fields GF (2 4 ) and GF ( (2 2 ) 2 ) is based on the primitive element in the higher order field GF (2 4 ). The recommended finite field S-box architecture is combinational and enables sub-pipelining. The linear and differential cryptanalysis validates that the proposed S-box is within the maximal security bound. It is observed that there is 86.5% lesser gate count for the realization of sub field operations in the composite field GF ( (2 2 ) 2 ) compared to the GF (2 4 ) field. In the PRESENT lightweight cipher structure with the basic loop architecture, the proposed S-box demonstrates 5% reduction in the gate equivalent area over the look-up-table-based S-box with TSMC 180 nm technology.

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High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs

Cited by 4 publications

References 28 publications

Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

Resource Optimized Security Coding In Light Weight Security Protocol

Lightweight S-Box Architecture for Secure Internet of Things

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