The SEU Risk Assessment of Z80A, 8086 and 80C86 Microprocessors Intended for Use in a Low Altitude Polar Orbit

Harboe-Sørensen, R.; Adams, L.; Daly, E.; Sansoè, Claudio; Mapper, D.; Sanderson, T. K.

doi:10.1109/tns.1986.4334653

Cited by 37 publications

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“…For example, using the CREME program [2] the upset rate for several single-chip microprocessors was shown to be between 1.2 10 -4 /hour and 8.4 10 -4 /hour (784 km 98° orbit, 1g/cm 2 Al shielding, solar minimum weather). For the worst case solar flare, the rates increased to between 3 and 18 upsets per hour [12]. As another example, the on-chip RAM of the INMOS Transputer was found to contribute almost 95% of the observed SEUs.…”

Section: Seu Fault Ratesmentioning

confidence: 97%

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System effects of single event upsets

Finn¹

1989

7th Computers in Aerospace Conference

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At the system level, SEUs in processors are controlled by fault-tolerance techniques such as replication and voting, watchdog processors, and tagged data schemes [13,16,30]. SEUs in memory subsystems are controlled by use of error control codes (ECCs) [4,17,21] and a process called scrubbing. The scrubbing process periodically reads each word in the memory. If the number of faulty digits in a word is less than or equal to the number the ECC can correct, then the digits are corrected and the word is written back to memory. If the number of faulty digits exceeds the ECC's capability, the errors cannot be corrected and the memory has failed. Fault-tolerance to memory failures requires either physical redundancy via replication or temporal redundancy via checkpoint rollback schemes. In most aerospace applications physical redundancy is undesirable because mass, volume, and power are at a premium.The rate at which SEUs are scrubbed from memory affects the performance and reliability of the entire computer system. Infrequent scrubbing leads to an accumulation of faults and increases the probability of exceeding the ECC's capability. Conversely, frequent scrubbing uses memory cycles that might otherwise be used by the operating system or an application program.There is a recognized tradeoff between using ECCs and scrubbing or using lower density, higher power, radiation-hardened semiconductors to achieve reliability [7,32]. Previous analyses of the tradeoffs between the use of simple ECCs, the additional hardware for the ECC, failure due to that additional hardware, and the system impact have been based on simplified analytical models; detailed analytical models are intractable.This paper introduces the idea of Markov modeling for SEU effects. Markov modeling allows extrapolation of chip failure rates to the subsystem and system level, allows more sophisticated tradeoff evaluations, and permits sensitivity analyses. The remainder of this paper is organized in three parts. Section 2 provides background about the SEU problem, expected SEU failure rates, and SEU control techniques. Section 3 introduces the use of Markov modeling techniques for memory subsystems and develops one model in detail. Section 4 presents the modeling results and generalizes the applicability of the modeling techniques.Single Event Upsets (SEUs) pose a serious threat to computer reliability and longevity. SEU effects are found at sea level, in airborne avionics, and in space. At the system level, SEUs in processors are controlled by replication and voting, watchdog processors, and tagged data schemes. SEUs in memory subsystems are controlled by periodically scrubbing words protected by an Error Control Code (ECC). The rate of memory scrubbing affects the performance and reliability of the entire computer system. There are tradeoffs between using radiation hardened semiconductors, scrubbing rates, and ECC capabilities. Previous tradeoff analyses have used simplified analytic models.The system effects of SEUs may be evaluated by Markov model...

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Section: Seu Fault Ratesmentioning

confidence: 97%

“…a Single Event Upset (SEU), in computer memory or combinational logic circuits. SEU effects are found at sea level [24,31], in airborne avionics [19,20], and in space [1,2,5,7,10,12,14,23,24,25,26,27,28,32]. The effect of SEUs on chips has been extensively investigated and programs, e.g.…”

Section: Introductionmentioning

confidence: 99%

System effects of single event upsets

Finn¹

1989

7th Computers in Aerospace Conference

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“…At this time, SETs did not compromise circuit functions compared to other radiation effects such as Total Ionizing Dose (TID). Several years, and maybe some decades, have been needed to highlight first soft errors observations [2] and then first SET evidences [3]- [5] in digital circuits. Then, SETs have never been out of the spotlight since technology scaling has pushed microelectronic circuits into deep submicron dimensions [6]- [9].…”

Section: Introductionmentioning

confidence: 99%

Modeling Single Event Transients in Advanced Devices and ICs

Artola

Gaillardin

Hubert

et al. 2015

IEEE Trans. Nucl. Sci.

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The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60's [1] and was confirmed to be a serious issue thirty years later. In the 90's microelectronic technologies reached the "deep submicron" era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the art of modeling at each scale, this paper will discuss current capabilities and intrinsic limitations of SET modeling, the incoming challenges in advanced devices and ICs, and finally the methodologies to improve SET simulation and prediction for future technologies.

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“…To obtain the system reliability, the probability that a particle cause a Single Event Upset (SEU) should be determined first. It can be shown that this probability is related with the device static cross section [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications

Brac¹,

Ferreyra²,

Velazco³

et al. 2009

2009 10th Latin American Test Workshop

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ISBN 978-1-4244-4207-2International audienceThis work presents a Fault Tolerant FPGA based Active Antenna system intended to be used in the space environment. The proposed design can control the electromagnetic radiation pattern emitted by an antenna array in real time with high reliability levels. The FPGA is a Commercial of the Shelf (COTS) device based on the Anti fuse technology. The design is optimized to reduce the area overhead allowing the control of multiple antennas by means of a single FPGA. The Fault Tolerance and high reliability achieved with the design is shown by means of a new test methodology

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The SEU Risk Assessment of Z80A, 8086 and 80C86 Microprocessors Intended for Use in a Low Altitude Polar Orbit

Cited by 37 publications

References 0 publications

System effects of single event upsets

System effects of single event upsets

Modeling Single Event Transients in Advanced Devices and ICs

Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications

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