The Second Generation MOTIS Mixed-Mode Simulator

Chen, C.F.; Lo, Chi-Yuan; Nham, H. N.; Subramaniam, P.

doi:10.1109/dac.1984.1585766

Cited by 42 publications

(3 citation statements)

References 7 publications

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“…Among logic level simulators, the RC switch-level model has been widely adopted since the model uniformly represents MOS device circuits well and may predict the circuit delay time with acceptable accuracy. Also according to Tsao [07], simulation modes can be classified as unit-delay mode, multiple-delay mode [09], timing mode [10] and the mixture of these modes [11].…”

Section: Historicalmentioning

confidence: 99%

Voltage controlled resistance model for MOS transistors

Jia¹

2000

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The voltage controlled resistance model is developed for a reliable MOS transistor resistance mapping. The model includes both system and local parameters, and incorporates the effect of rise and fall time variations on the gate delay. MOS transistor resistance mapping is applied in logic simulation and timing verification. Also, it can be used in automatic transistor sizing and critical path analysis.

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Section: Historicalmentioning

confidence: 99%

Voltage controlled resistance model for MOS transistors

Jia¹

2000

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“…Using a tit order integration algorithm, the node voltages at the next time point can be computed as Vc(fn+l) = vc(~n) +~c(ln)Atn + 1 (10) here Atn+l = t"+, -tn. If the approximate voltage slopes vc(tn) is used instead of tic(tn) asobtained by the exact inversion of the C matrix, then the node voltages will becomẽ c(tn+l) = Vc(fn)+ ;C(In)Afn + ,…”

Section: Thenmentioning

confidence: 99%

Simulation of coupling capacitances using matrix partitioning

Nguyen

Devgan

Sadigh³

1998

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '98

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Thispaperpresentsa matrLrpartitioning scheme for the simulation of coupling capacitances in timing and noise analysis. An error criten.on similar to the local truncation error of integration algorithms was developed to control the error due to this matriv partitioning algorithm.~e major advantage of the algorithm is that it does not require iterations such as required in rela~ation algon.thrns, and it is designed to work with circuit partitioning for eficient simulation of large circuits in fast circuitkiming simulator like ACES [lJ, which firms the basis for an eficient transistor level simulation and analysis. The mattipartitioning algorithm alsofits well with controlled evplicit integration algon"thms. Results demonstrate that the algon.thm can ensure simulation accuracy without signl~cantly degrading simulation eficiency for the timing and noise analysis of circuits designed in advanced technologies with small feature sizes.

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“…A node may, however, change voltage without a change of logic value; when this happens, an "event" is recognized provided that the voltage change is at least .4V. This primarily logic-driven scheduling distinguishes VTIsim from more accurate incremental simulators, such ss the original MOTIS [3,4], which schedule evaluations based on time or voltage increments.…”

Section: Schedulingmentioning

confidence: 99%

A Transistor-Level Logic-with-Timing Simulator for MOS Circuits

Schaefer¹

1985

22nd ACM/IEEE Design Automation Conference

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Abatra.ct.VTIsim is a transistor-level simulator for MOS circuits which provides logic simulation together with approximate timing estimates based on layout information. Two novel features enhance the accuracy of simulation: node states are represented as voltages rather than as logic states, and node transitions are modeled as voltage ramps rather than as steps taking place at a fixed instant. This paper describes the major features of the simulator, some issues in its design, and the benefits and problems of using it.

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The Second Generation MOTIS Mixed-Mode Simulator

Cited by 42 publications

References 7 publications

Voltage controlled resistance model for MOS transistors

Voltage controlled resistance model for MOS transistors

Simulation of coupling capacitances using matrix partitioning

A Transistor-Level Logic-with-Timing Simulator for MOS Circuits

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