The Scalable Coherent Interface and related standards projects

Gustavson, D.B.

doi:10.1109/40.124376

Cited by 142 publications

(37 citation statements)

References 11 publications

(1 reference statement)

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“…Our prototype has been implemented on a four-node cluster of dual-processors running Linux based on the scalable coherent interface (SCI) [14] interconnection technology. Nodes are based on Intel Pentium II (450 MHz) PCs and have a 256 Mbyte local memory.…”

Section: Methodsmentioning

confidence: 99%

HA‐PSLS: a highly available parallel single‐level store system

Kermarrec

Morin

2003

Concurrency and Computation

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SUMMARYParallel single-level store (PSLS) systems integrate a shared virtual memory and a parallel file system. They provide programmers with a global address space including both memory and file data. PSLS systems implemented in a cluster thus represent a natural support for long-running parallel applications, combining both the natural shared memory programming model and a large and efficient file system. However, the need to tolerate failures in such a system increases with the size of applications. In this paper we present a highly-available parallel single level store system (HA-PSLS), which smoothly integrates a backward error recovery high-availability mechanism into a PSLS system. Our system is able to tolerate multiple transient failures, a single permanent failure, and power cut failures affecting the whole cluster, without requiring any specialized hardware. For this purpose, HA-PSLS relies on a high degree of integration (and reusability) of high-availability and standard features. A prototype integrating our highavailability support has been implemented and we show some performance results in the paper. Copyright

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Section: Methodsmentioning

confidence: 99%

HA‐PSLS: a highly available parallel single‐level store system

Kermarrec

Morin

2003

Concurrency and Computation

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“…These protocols (also known as chained directory protocols), such as the IEEE Standard Scalable Coherent Interface (SCI) [11], rely on distributing the sharing code among the nodes of the system. For every one of its memory lines, the home node contains only a pointer to the first sharer in the list plus a few state bits.…”

Section: Cache-based Directory Protocolsmentioning

confidence: 99%

A two-level directory architecture for highly scalable cc-NUMA multiprocessors

Acacio

González

Garcia

et al. 2005

IEEE Trans. Parallel Distrib. Syst.

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Abstract-One important issue the designer of a scalable shared-memory multiprocessor must deal with is the amount of extra memory required to store the directory information. It is desirable that the directory memory overhead be kept as low as possible, and that it scales very slowly with the size of the machine. Unfortunately, current directory architectures provide scalability at the expense of performance. This work presents a scalable directory architecture that significantly reduces the size of the directory for large-scale configurations of a multiprocessor without degrading performance. First, we propose multilayer clustering as an effective approach to reduce the width of directory entries. Based on this concept, we derive three new compressed sharing codes, some of them with a space complexity of O log 2 log 2 N ð Þ ð Þ ð Þ for an N-node system. Then, we present a novel two-level directory architecture to eliminate the penalty caused by compressed directories in general. The proposed organization consists of a small full-map first-level directory (which provides precise information for the most recently referenced lines) and a compressed second-level directory (which provides inexcess information for all the lines). The proposals are evaluated based on extensive execution-driven simulations (using RSIM) of a 64-node cc-NUMA multiprocessor. Results demonstrate that a system with a two-level directory architecture achieves the same performance as a multiprocessor with a big and nonscalable full-map directory, with a very significant reduction of the memory overhead.

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“…A previous system, SCI (Scalable Coherent Interface) [20], also uses rings, and can be configured in many topologies (including hierarchical rings). However, to handle buffer-full conditions, SCI NACKs and subsequently retransmits packets, whereas HiRD deflects only single flits (within a ring), and does not require the sender to retransmit its flits.…”

Section: E Comparison Against Other Ring Configurationsmentioning

confidence: 99%

Design and Evaluation of Hierarchical Rings with Deflection Routing

Ausavarungnirun

Fallin

et al. 2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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Abstract-Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarchical ring designs sacrifice some of the key benefits of rings by reintroducing more complex in-ring buffering and buffered flow control. Our goal in this paper is to design a new hierarchical ring interconnect that can maintain most of the simplicity of traditional ring designs (i.e., no in-ring buffering or buffered flow control) while achieving high scalability as more complex buffered hierarchical ring designs.To this end, we revisit the concept of a hierarchical-ring networkon-chip. Our design, called HiRD (Hierarchical Rings with Deflection), includes critical features that enable us to mostly maintain the simplicity of traditional simple ring topologies while providing higher energy efficiency and scalability. First, HiRD does not have any buffering or buffered flow control within individual rings, and requires only a small amount of buffering between the ring hierarchy levels. When inter-ring buffers are full, our design simply deflects flits so that they circle the ring and try again, which eliminates the need for in-ring buffering. Second, we introduce two simple mechanisms that together provide an end-to-end delivery guarantee within the entire network (despite any deflections that occur) without impacting the critical path or latency of the vast majority of network traffic.Our experimental evaluations on a wide variety of multiprogrammed and multithreaded workloads and synthetic traffic patterns show that HiRD attains equal or better performance at better energy efficiency than multiple versions of both a previous hierarchical ring design and a traditional single ring design. We also extensively analyze our design's characteristics and injection and delivery guarantees. We conclude that HiRD can be a compelling design point that allows higher energy efficiency and scalability while retaining the simplicity and appeal of conventional ring-based designs.

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The Scalable Coherent Interface and related standards projects

Cited by 142 publications

References 11 publications

HA‐PSLS: a highly available parallel single‐level store system

HA‐PSLS: a highly available parallel single‐level store system

A two-level directory architecture for highly scalable cc-NUMA multiprocessors

Design and Evaluation of Hierarchical Rings with Deflection Routing

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