A two-level directory architecture for highly scalable cc-NUMA multiprocessors

Acacio, Manuel E.; González, José María Faci; Garcia, Jose M.; Duato, J.

doi:10.1109/tpds.2005.4

Cited by 39 publications

(20 citation statements)

References 32 publications

(40 reference statements)

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“…In [1], [2] a two-level cache directory is proposed. The first-level stores the typical sharer vector while the second-level uses a compressed code.…”

Section: Related Workmentioning

confidence: 99%

PS directory: a scalable multilevel directory cache for CMPs

et al. 2014

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Abstract-As the number of cores increases in current and future chip-multiprocessor (CMP) generations, coherence protocols must rely on novel hardware structures in order to scale in terms of performance, power, and area. Systems that use directory information for coherence purposes are currently the most scalable alternative. This paper studies the important differences between the directory behavior of private and shared blocks, which claim for a separate management of both types of blocks at the directory. We propose the PS directory, a two-level directory cache that keeps the reduced number of frequently accessed shared entries in a small and fast first-level cache, namely Shared cache, and uses a larger and slower second-level Private cache to track the large amount of private blocks. Entries in the Private cache do not implement the sharer vector, which allows important silicon area savings.Speed and area reasons suggest the use of eDRAM technology, much denser but slower than SRAM technology, for the Private cache, which in turn brings energy savings. Experimental results for a 16-core CMP show that, compared to a conventional directory, the PS directory improves performance by 14% while reducing silicon area and energy consumption by 34% and 27%, respectively. Also, compared to the state-of-the-art Multi-Grain Directory, the PS directory apart from increasing performance, it reduces power by 18.7%, and provides more scalability in terms of area.

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“…In [1], [2] a two-level cache directory is proposed. The first-level stores the typical sharer vector while the second-level uses a compressed code.…”

Section: Related Workmentioning

confidence: 99%

PS directory: a scalable multilevel directory cache for CMPs

et al. 2014

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“…These protocols employ the inclusion property, and in [7], several conditions for imposing the inclusion property for fully and set-associative cache hierarchies are presented. Recently, attention has turned to architectures that support CMP's with variable degrees of hierarchy [1][2][3]8,9,21,29,35,38]. Acacio et al [3] propose a hierarchical scheme for directory-based consistency using a multilayer clustering concept.…”

Section: Related Workmentioning

confidence: 99%

A consistency architecture for hierarchical shared caches

Ladan-Mozes

Leiserson

2008

Proceedings of the Twentieth Annual Symposium on Parallelism in Algorithms and Architectures

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Hierarchical Cache Consistency (HCC) is a scalable cache-consistency architecture for chip multiprocessors in which caches are shared hierarchically. HCC's cache-consistency protocol is embedded in the message-routing network that interconnects the caches, providing a distributed and scalable alternative to bus-based and directory-based consistency mechanisms. The HCC consistency protocol is "progressive" in that every message makes monotonic progress without timeouts, retries, negative acknowledgments, or retreating in any way. The latency is at most proportional to the diameter of the network. For HCC with a binary fat-tree network, the protocol requires at most 13 bits of additional state per cache line, no matter how large the system. We prove that the HCC protocol is deadlock free and provides sequential consistency.

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“…An additional benefit of our proposal is that we completely remove directory information from main memory, saving memory space. This directory information represents an overhead in the memory size from the 3% in the SGI Altix 3000 [20] to 12% in other systems, and could even reach 100% [3] depending of both the sharing code and the number of nodes used.…”

Section: Proposed Cache Designmentioning

confidence: 99%

An efficient cache design for scalable glueless shared-memory multiprocessors

Ros

Acacio

García

2006

Proceedings of the 3rd Conference on Computing Frontiers

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Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the access to main memory to recover the sharing status of the block is generally put in the critical path of every cache miss, increasing its latency. Considering the ever-increasing distance to memory, these cache coherence protocols are far from being optimal from the perspective of performance. On the other hand, shared-memory multiprocessors formed by connecting chips that integrate the processor, caches, coherence logic, switch and memory controller through a low-cost, low-latency point-to-point network (glueless shared-memory multiprocessors) are a reality.In this work, we propose a novel design for the L2 cache level, at which coherence has to be maintained, aimed at being used in glueless shared-memory multiprocessors. Our proposal splits the cache structure into two different parts: one for storing data and directory information for the blocks requested by the local processor, and another one for storing only directory information for blocks accessed by remote processors. Using this cache scheme we remove the directory from main memory. Besides saving memory space, our proposal brings very significant reductions in terms of latency of the cache misses (speed-ups of 3.0 on average), which translate into reductions in applications' execution time of 31% on average.

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A two-level directory architecture for highly scalable cc-NUMA multiprocessors

Cited by 39 publications

References 32 publications

PS directory: a scalable multilevel directory cache for CMPs

PS directory: a scalable multilevel directory cache for CMPs

A consistency architecture for hierarchical shared caches

An efficient cache design for scalable glueless shared-memory multiprocessors

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