The Role of FPGAs in the Push to Modern and Ubiquitous Arrays

Miller, Luke

doi:10.1109/jproc.2016.2519286

Cited by 5 publications

(1 citation statement)

References 6 publications

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“…Although element-level digitization enables the development of software-defined phased array radars, extremely high input/output (I/O) bandwidths are occupied by digitized T/R waveforms; consequently, powerful signal processors are required for real-time computing. Benefiting considerably from the shrinking CMOS technology node, field-programmable gate arrays (FPGAs) are equipped with excellent performance per watt, high-speed interfaces, and parallel computing capabilities at reasonable costs and time to market [30,31]. With features of low latency and reduced data throughput, a hierarchical digital beamforming topology [2,9,10,32] has been implemented in FPGAs and employed for real-time radar imaging.…”

Section: Introductionmentioning

confidence: 99%

An X-Band CMOS Digital Phased Array Radar from Hardware to Software

Chou

et al. 2021

Sensors

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Phased array technology features rapid and directional scanning and has become a promising approach for remote sensing and wireless communication. In addition, element-level digitization has increased the feasibility of complicated signal processing and simultaneous multi-beamforming processes. However, the high cost and bulky characteristics of beam-steering systems have prevented their extensive application. In this paper, an X-band element-level digital phased array radar utilizing fully integrated complementary metal-oxide-semiconductor (CMOS) transceivers is proposed for achieving a low-cost and compact-size digital beamforming system. An 8–10 GHz transceiver system-on-chip (SoC) fabricated in 65 nm CMOS technology offers baseband filtering, frequency translation, and global clock synchronization through the proposed periodic pulse injection technique. A 16-element subarray module with an SoC integration, antenna-in-package, and tile array configuration achieves digital beamforming, back-end computing, and dc–dc conversion with a size of 317 × 149 × 74.6 mm3. A radar demonstrator with scalable subarray modules simultaneously realizes range sensing and azimuth recognition for pulsed radar configurations. Captured by the suggested software-defined pulsed radar, a complete range–azimuth figure with a 1 km maximum observation range can be displayed within 150 ms under the current implementation.

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