The Road towards Predictable Automotive High - Performance Platforms

Abstract

Due to the trends of centralizing the E/E architecture and new computing-intensive applications, high-performance hardware platforms are currently finding their way into automotive systems. However, the SoCs currently available on the market have significant weaknesses when it comes to providing predictable performance for time-critical applications. The main reason for this is that these platforms are optimized for averagecase performance. This shortcoming represents one major risk in the development of current and future automotive systems. In this paper we describe how high-performance and predictability could (and should) be reconciled in future HW/SW platforms. We believe that this goal can only be reached in a close collaboration between system suppliers, IP providers, semiconductor companies, and OS/hypervisor vendors. Furthermore, academic input will be needed to solve remaining challenges and to further improve initial solutions.

A Universidade do Minho em tempos de pandemia: Tomo I: Reflexões

“…While the latter could be solved by employing cache bleaching [57] in heterogeneous platforms, to further minimize coloring bottlenecks, we advocate for SPH to adopt other proven, widely applicable contention mitigation mechanisms, e.g., bandwidth regulation mechanisms implemented via PMU-based CPU throttling [58], [59]. We also stress the importance of including support for hardware extensions such as Arm's Memory Partitioning and Monitoring (MPAM) [11], [60], which provide flexible hardware means for partitioning cache space and memory bandwidth and call for platform designers to include such facilities in their upcoming designs targeting MCS. Finally, we stress the need for instrumentation, analysis, and profiling tools [20], [61] that integrate with these hypervisors to help system designers understand the trade-offs and fine-tune these mechanisms (e.g., through automation).…”

“…While traditional hypervisors were optimized for the latter [5], [6], on the opposite end of the spectrum we have static partitioning hypervisors (SPH) specifically designed for MCS [7], [8]. Besides statically assigning system resources (e.g., CPUs, memory, or devices) to virtual machines (VMs), SPH must provide latency and isolation guarantees at the microarchitectural level to comply with the freedom from interference requirements of industry safety standards such as ISO 26262 [1], [9]- [11].…”

Computationally Efficient Worst-Case Analysis of Flow-Controlled Networks With Network Calculus

“…The latter is a theory for deterministic network evaluation, which dates back to the early 1990s, and it is mainly due to the work of Cruz [7], [8], Le Boudec and Thiran [9], and Chang [10]. Originally devised for the Internet, where it was used to engineer models of service [11]- [15], it has found applications in several other contexts, from sensor networks [16] to avionic networks [17], [18], industrial networks [19]- [21], automotive systems [22] and systems architecture [23], [24]. Its main strength is that it allows one to compute worst-case delay bounds in systems with multi-hop traversal.…”

Extending the Network Calculus Algorithmic Toolbox for Ultimately Pseudo-Periodic Functions: Pseudo-Inverse and Composition

“…NC dates back to the early 1990s, and it is mainly due to the work of Cruz [1,2], Le Boudec and Thiran [3], and Chang [4]. Originally devised for the Internet, where it was used to engineer models of service [5][6][7][8][9], it has found applications in several other contexts, from sensor networks [10] to avionic networks [11,12], industrial networks [13][14][15] automotive systems [16] and systems architecture [17,18].…”