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In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.
In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.
The expansion of mobile connectivity with the arrival of 6G paves the way for the new Internet of Verticals (6G-IoV), benefiting autonomous driving. This article highlights the importance of vehicle-to-everything (V2X) and vehicle-to-vehicle (V2V) communication in improving road safety. Current technologies such as IEEE 802.11p and LTE-V2X are being improved, while new radio access technologies promise more reliable, lower-latency communications. Moreover, 3GPP is developing NR-V2X to improve the performance of communications between vehicles, while IEEE proposes the 802.11bd protocol, aiming for the greater interoperability and detection of transmissions between vehicles. Both new protocols are being developed and improved to make autonomous driving more efficient. This study analyzes and compares the performance of the protocols mentioned, namely 802.11p, 802.11bd, LTE-V2X, and NR-V2X. The contribution of this study is to identify the most suitable protocol that meets the requirements of V2V communications in autonomous driving. The relevance of V2V communication has driven intense research in the scientific community. Among the various applications of V2V communication are Cooperative Awareness, V2V Unicast Exchange, and V2V Decentralized Environmental Notification, among others. To this end, the performance of the Link Layer of these protocols is evaluated and compared. Based on the analysis of the results, it can be concluded that NR-V2X outperforms IEEE 802.11bd in terms of transmission latency (L) and data rate (DR). In terms of the packet error rate (PER), it is shown that both LTE-V2X and NR-V2X exhibit a lower PER compared to IEEE protocols, especially as the distance between the vehicles increases. This advantage becomes even more significant in scenarios with greater congestion and network interference.
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