The RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems

Abstract

Embedded systems increasingly combine multi-core processors and heterogeneous resources such as graphics-processing units and field-programmable gate arrays. However, significant application design complexity for such systems caused by parallel programming and device-specific challenges has often led to untapped performance potential. Application developers targeting such systems currently must determine how to parallelize computation, create different device-specialized implementations for each heterogeneous resource, and then determine how to apportion work to each resource. In this paper, we present the RACECAR heuristic to automate the optimization of applications for multi-core heterogeneous systems by automatically exploring implementation alternatives that include different algorithms, parallelization strategies, and work distributions. Experimental results show RACECAR-specialized implementations can effectively incorporate provided implementations and parallelize computation across multiple cores, graphics-processing units, and field-programmable gate arrays, improving performance by an average of 47x compared to a CPU, while the fastest provided implementations are only able to average 33x.

Elastic Management of Reconfigurable Accelerators

“…For instance, a different concept of elasticity named elastic computing has been introduced [8] which supports portable designs (the ability to run one function on multiple platforms) but augmented with a selection model which can choose the best available implementation based on application properties, and pre-compiled performance models. The authors extend their work in [9] which introduces a heuristic for generating parallel implementations for heterogeneous computers.…”

A framework for dynamic parallelization of FPGA-accelerated applications

“…Performance information on each function is made available by implementation performance graphs (IPGs) similar to those described in [31], although any form of performance prediction could potentially be used. IPGs contain the execution times for a function implementation at a variety of input sizes.…”

“…Lastly, our implementation of the scheduler does not consider intra-function parallelization optimizations, such as parallelizing a single function across multiple CPU cores using divide-andconquer techniques (e.g., [31]). Such optimizations are compatible with our approach and will be merged with our framework in the future.…”